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参数资料
| 型号： | ENC28J60T-I/SS |
| 厂商： | Microchip Technology |
| 文件页数： | 11/12页 |
| 文件大小： | 0K |
| 描述： | IC ETHERNET CTLR SPI 28SSOP |
| 标准包装： | 1 |
| 控制器类型： | 以太网控制器，MAC/10Base-T |
| 接口： | SPI |
| 电源电压： | 3.1 V ~ 3.6 V |
| 电流 - 电源： | 160mA |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 28-SSOP（0.209"，5.30mm 宽） |
| 供应商设备封装： | 28-SSOP |
| 包装： | 标准包装 |
| 产品目录页面： | 684 (CN2011-ZH PDF) |
| 其它名称： | ENC28J60T-I/SSDKR |
ENC28J60
DS80349C-page 8
2010 Microchip Technology Inc.
Ethernet Conformance Issues
The following conformance issues were noted in testing
the B1 and B4 silicon revisions for compliance with IEEE
Standard 802.3. These issues are not present after
Revision B4 and are included for informational purposes.
1. Issue:
TP_IDL Pattern
The observed TP_IDL pattern transmitted by
ENC28J60 was observed to not stay within the
standard defined template when using the TPM
(Twisted Pair Model) and TP Test Load 2.
Reference:
IEEE
Std
802.3,
§14.3.1.2.1,
Figures 14-10 and 14-11
Potential Application Impact
The TP_IDL test requires a total of six separate
subtests, using three different test loads with and
without TPM. The fact that the device consistently
passed five of the six sub tests, while narrowly
missing the sixth, leads to the conclusion that this
is a minor issue. No failures have been observed
due to this issue.
Work around
Use silicon revision B5 or later.
Affected Silicon Revisions
2. Issue:
Exiting Link Test Fail State
The ENC28J60 was observed to improperly
accept a frame with no preceding LTPs (Link Test
Pulse). When a device is in the Link Test Fail state,
it should exit this state when a valid packet is
received, however, the first packet should not be
accepted. The second and subsequent packets
should be accepted while the device is in the Link
Test Pass state.
Reference: IEEE Std 802.3, Figure 14-6
Potential Application Impact
Link Test Pulse is an integral part of every
10Base-T system. It is used to notify a link partner
of the presence of a 10Base-T device. An absence
of LTPs signifies that the Ethernet cable is not con-
nected or a link partner is missing. Even when a
cable is not connected, a 10Base-T device would
continuously send out LTPs. This fact makes it
unlikely that there will ever be a situation in which
a device would be receiving valid Ethernet frames
without already being in the Link Test Pass state.
In the unlikely event that this situation does occur,
higher layer protocols would protect the system
from accepting unwanted data. It is unlikely that
this failure will have significant impact on a
networked application. No failures have been
observed due to this issue.
Work around
Use silicon revision B5 or later.
Affected Silicon Revisions
3. Issue:
Collision Handling
The delay from the collision event to collision
enforcement with the jam pattern is approximately
50 BT (Bit Times), which is greater than the
specified limit of 36 BT.
Reference: IEEE Std 802.3, Annex B, § B.1.2
Potential Application Impact
A collision in a half-duplex 10Base-T is not an
unexpected event. It exists as a normal part of the
network operation. The purpose of the jam pattern
is to ensure that the duration of the collision is
sufficient to be noticed by the other transmitting
station(s) involved in the collision. A longer delay
between the collision event and the start of jam
pattern would cause the duration of the collision to
be longer.
After each collision, both transmitting stations
would back off and wait a random amount of time
before attempting to transmit again. The minimum
Idle time between each Ethernet frame is 9.6
s.
The longer collision duration of 14 BT, or 1.4
s,
can be considered as a small fraction of time
wasted for each collision. It is unlikely that this
issue will have significant impact on networked
applications. No failures have been observed due
to this issue.
Work around
Use silicon revision B5 or later.
Affected Silicon Revisions
B1
B4
B5
B7
XX
B1
B4
B5
B7
XX
B1
B4
B5
B7
XX
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