参数资料
型号: EP1C3T100A8N
厂商: Altera
文件页数: 46/78页
文件大小: 0K
描述: IC CYCLONE FPGA 2910 LE 100-TQFP
产品培训模块: Three Reasons to Use FPGA's in Industrial Designs
标准包装: 180
系列: Cyclone®
LAB/CLB数: 291
逻辑元件/单元数: 2910
RAM 位总计: 59904
输入/输出数: 65
电源电压: 1.425 V ~ 1.575 V
安装类型: 表面贴装
工作温度: 0°C ~ 85°C
封装/外壳: 100-TQFP
供应商设备封装: 100-TQFP(14x14)
7–4
Chapter 7: HardCopy II Devices
Pin-Out Information
Altera Corporation
f For more information about the DC characteristics of the industrial-grade
HardCopy II devices, refer to the DC and Switching Specifications and Operating
Conditions chapter in volume 1 of the HardCopy II Device Handbook.
However, the following exceptions apply:
The delay-locked loop (DLL) frequency range is bounded by the minimum
frequencies listed in Table 7–2.
Table 7–2 lists the minimum DLL frequency for each frequency mode.
Non-calibrated on-chip termination (OCT) is bounded by:
±40% for series resistance.
±50% for 1.2-V series resistance.
Hot-socketing DC limit is raised to 350 A.
The I/O fMAX values of automotive-grade HardCopy II devices are 15% lower than
their equivalent industrial-grade HardCopy II devices and correspond to the
commercial-grade Stratix II devices of –5 speed. The I/O fMAX values of the
industrial-grade HardCopy II devices will be updated in a later revision of the
HardCopy II Device Handbook.
f For the maximum I/O clock toggle rate specifications in commercial-grade Stratix II
devices of –5 speed, refer to the DC and Switching Characteristics chapter in volume 1 of
the Stratix II Device Handbook.
For LVDS I/O of 2.5 V, the minimum VOCM is 1.1 V and the minimum differential
output voltage (VOD) is 240 mV.
Pin-Out Information
f For more information about the HardCopy II device pin-outs, refer to the
Table 7–2. Minimum DLL Frequency
Mode
Frequency (MHz)
Frequency Mode 0
120
Frequency Mode 1
170
Frequency Mode 2
220
Frequency Mode 3
270
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