参数资料
型号: EP1C4T144I8ES
厂商: Altera Corporation
英文描述: Cyclone FPGA Family Data Sheet
中文描述: 气旋的FPGA系列数据手册
文件页数: 100/104页
文件大小: 763K
代理商: EP1C4T144I8ES
4–30
Preliminary
Altera Corporation
January 2007
Cyclone Device Handbook, Volume 1
f
OUT
(to global clock)
PLL output fre
q
uency
(-6 speed grade)
15.625
405
MHz
PLL output fre
q
uency
(-7 speed grade)
15.625
320
MHz
PLL output fre
q
uency
(-8 speed grade)
15.625
275
MHz
t
OUT
DUTY
Duty cycle for external clock
output (when set to 50
%
)
45.00
55
%
t
JITTER
(1)
Period jitter for external clock
output
±300
(2)
ps
t
LOCK
(3)
Time re
q
uired to lock from end
of device configuration
10.00
100
μ
s
f
VCO
PLL internal VCO operating
range
500.00
1,000
MHz
-
Minimum areset time
10
ns
N
, G0, G1, E
Counter values
1
32
integer
Notes to
Table 4–52
:
(1)
The t
JITTER
specification for the
PLL[2..1]_OUT
pins are dependent on the I/O pins in its V
CCIO
bank, how many
of them are switching outputs, how much they toggle, and whether or not they use programmable current strength
or slow slew rate.
(2)
f
OUT
100 MHz. When the PLL external clock output frequency (f
OUT
) is smaller than 100 MHz, the jitter
specification is 60 mUI.
(3)
f
IN/N
must be greater than 200 MHz to ensure correct lock detect circuit operation below –20 C. Otherwise, the PLL
operates with the specified parameters under the specified conditions.
Table 4–52. Cyclone PLL Specifications (Part 2 of 2)
Symbol
Parameter
Min
Max
Unit
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