参数资料
型号: EP1C4T144I8ES
厂商: Altera Corporation
英文描述: Cyclone FPGA Family Data Sheet
中文描述: 气旋的FPGA系列数据手册
文件页数: 60/104页
文件大小: 763K
代理商: EP1C4T144I8ES
2–54
Preliminary
Altera Corporation
January 2007
Cyclone Device Handbook, Volume 1
Each I/O bank can support multiple standards with the same V
CCIO
for
input and output pins. For example, when V
CCIO
is 3.3-V, a bank can
support LVTTL, LVCMOS, 3.3-V PCI, and SSTL-3 for inputs and outputs.
LVDS I/O Pins
A subset of pins in all four I/O banks supports LVDS interfacing. These
dual-purpose LVDS pins require an external-resistor network at the
transmitter channels in addition to 100-
Ω
termination resistors on receiver
channels. These pins do not contain dedicated serialization or
deserialization circuitry; therefore, internal logic performs serialization
and deserialization functions.
Table 2–13
shows the total number of supported LVDS channels per
device density.
MultiVolt I/O Interface
The Cyclone architecture supports the MultiVolt I/O interface feature,
which allows Cyclone devices in all packages to interface with systems of
different supply voltages. The devices have one set of V
CC
pins for
internal operation and input buffers (V
CCINT
), and four sets for I/O
output drivers (V
CCIO
).
Table 2–13. Cyclone Device LVDS Channels
Device
Pin Count
Number of LVDS Channels
EP1C3
100
(1)
144
34
EP1C4
324
103
400
129
EP1C6
144
29
240
72
256
72
EP1C12
240
66
256
72
324
103
EP1C20
324
95
400
129
Note to
Table 2–13
:
(1)
EP1C3 devices in the 100-pin TQFP package do not support the LVDS I/O
standard.
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