参数资料
型号: EP1C4T240C8ES
厂商: Altera Corporation
英文描述: Cyclone FPGA Family Data Sheet
中文描述: 气旋的FPGA系列数据手册
文件页数: 45/104页
文件大小: 763K
代理商: EP1C4T240C8ES
Altera Corporation
January 2007
2–39
Preliminary
I/O Structure
I/O Structure
IOEs support many features, including:
Differential and single-ended I/O standards
3.3-V, 64- and 32-bit, 66- and 33-MHz PCI compliance
Joint Test Action Group (JTAG) boundary-scan test (BST) support
Output drive strength control
Weak pull-up resistors during configuration
Slew-rate control
Tri-state buffers
Bus-hold circuitry
Programmable pull-up resistors in user mode
Programmable input and output delays
Open-drain outputs
DQ and DQS I/O pins
Cyclone device IOEs contain a bidirectional I/O buffer and three registers
for complete embedded bidirectional single data rate transfer.
Figure 2–27
shows the Cyclone IOE structure. The IOE contains one input
register, one output register, and one output enable register. You can use
the input registers for fast setup times and output registers for fast clock-
to-output times. Additionally, you can use the output enable (OE) register
for fast clock-to-output enable timing. The Quartus II software
automatically duplicates a single OE register that controls multiple
output or bidirectional pins. IOEs can be used as input, output, or
bidirectional pins.
相关PDF资料
PDF描述
EP1C4T240I6ES Cyclone FPGA Family Data Sheet
EP1C4T240I8ES Cyclone FPGA Family Data Sheet
EP1C4T256C6ES Cyclone FPGA Family Data Sheet
EP1C4T256C7ES Cyclone FPGA Family Data Sheet
EP1C4T256C8ES Cyclone FPGA Family Data Sheet
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