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| 型号： | EP1C4T240C8ES |
| 厂商： | Altera Corporation |
| 英文描述： | Cyclone FPGA Family Data Sheet |
| 中文描述： | 气旋的FPGA系列数据手册 |
| 文件页数： | 68/104页 |
| 文件大小： | 763K |
| 代理商： | EP1C4T240C8ES |
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3–6
Preliminary
Altera Corporation
January 2007
Cyclone Device Handbook, Volume 1
Operating Modes
The Cyclone architecture uses SRAM configuration elements that require
configuration data to be loaded each time the circuit powers up. The
process of physically loading the SRAM data into the device is called
configuration. During initialization, which occurs immediately after
configuration, the device resets registers, enables I/O pins, and begins to
operate as a logic device. Together, the configuration and initialization
processes are called command mode. Normal device operation is called
user mode.
SRAM configuration elements allow Cyclone devices to be reconfigured
in-circuit by loading new configuration data into the device. With real-
time reconfiguration, the device is forced into command mode with a
device pin. The configuration process loads different configuration data,
reinitializes the device, and resumes user-mode operation. Designers can
perform in-field upgrades by distributing new configuration files either
within the system or remotely.
A built-in weak pull-up resistor pulls all user I/O pins to V
CCIO
before
and during device configuration.
The configuration pins support 1.5-V/1.8-V or 2.5-V/3.3-V I/O
standards. The voltage level of the configuration output pins is
determined by the V
CCIO
of the bank where the pins reside. The bank
V
CCIO
selects whether the configuration inputs are 1.5-V, 1.8-V, 2.5-V, or
3.3-V compatible.
Configuration Schemes
Designers can load the configuration data for a Cyclone device with one
of three configuration schemes (see
Table 3–5
), chosen on the basis of the
target application. Designers can use a configuration device, intelligent
controller, or the JTAG port to configure a Cyclone device. A low-cost
configuration device can automatically configure a Cyclone device at
system power-up.
相关PDF资料 |
PDF描述 |
|---|---|
| EP1C4T240I6ES | Cyclone FPGA Family Data Sheet |
| EP1C4T240I8ES | Cyclone FPGA Family Data Sheet |
| EP1C4T256C6ES | Cyclone FPGA Family Data Sheet |
| EP1C4T256C7ES | Cyclone FPGA Family Data Sheet |
| EP1C4T256C8ES | Cyclone FPGA Family Data Sheet |
相关代理商/技术参数 |
参数描述 |
|---|---|
| EP1C6F256C6 | 功能描述:FPGA - 现场可编程门阵列 FPGA - Cyclone I 598 LABs 185 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| EP1C6F256C6N | 功能描述:FPGA - 现场可编程门阵列 FPGA - Cyclone I 598 LABs 185 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| EP1C6F256C7 | 功能描述:FPGA - 现场可编程门阵列 FPGA - Cyclone I 598 LABs 185 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| EP1C6F256C7N | 功能描述:FPGA - 现场可编程门阵列 FPGA - Cyclone I 598 LABs 185 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| EP1C6F256C8 | 功能描述:FPGA - 现场可编程门阵列 FPGA - Cyclone I 598 LABs 185 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
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