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| 型号： | EP1C6T144I8ES |
| 厂商： | Altera Corporation |
| 英文描述： | Cyclone FPGA Family Data Sheet |
| 中文描述： | 气旋的FPGA系列数据手册 |
| 文件页数： | 52/104页 |
| 文件大小： | 763K |
| 代理商： | EP1C6T144I8ES |
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2–46
Preliminary
Altera Corporation
January 2007
Cyclone Device Handbook, Volume 1
to automatically minimize setup time while providing a zero hold time.
Programmable delays can increase the register-to-pin delays for output
registers.
Table 2–9
shows the programmable delays for Cyclone devices.
There are two paths in the IOE for a combinatorial input to reach the logic
array. Each of the two paths can have a different delay. This allows you
adjust delays from the pin to internal LE registers that reside in two
different areas of the device. The designer sets the two combinatorial
input delays by selecting different delays for two different paths under
the
Decrease input delay to internal cells
logic option in the Quartus II
software. When the input signal requires two different delays for the
combinatorial input, the input register in the IOE is no longer available.
The IOE registers in Cyclone devices share the same source for clear or
preset. The designer can program preset or clear for each individual IOE.
The designer can also program the registers to power up high or low after
configuration is complete. If programmed to power up low, an
asynchronous clear can control the registers. If programmed to power up
high, an asynchronous preset can control the registers. This feature
prevents the inadvertent activation of another device's active-low input
upon power up. If one register in an IOE uses a preset or clear signal then
all registers in the IOE must use that same signal if they require preset or
clear. Additionally a synchronous reset signal is available to the designer
for the IOE registers.
External RAM Interfacing
Cyclone devices support DDR SDRAM and FCRAM interfaces at up to
133 MHz through dedicated circuitry.
DDR SDRAM & FCRAM
Cyclone devices have dedicated circuitry for interfacing with DDR
SDRAM. All I/O banks support DDR SDRAM and FCRAM I/O pins.
However, the configuration input pins in bank 1 must operate at 2.5 V
because the SSTL-2 V
CCIO
level is 2.5 V. Additionally, the configuration
Table 2–9. Cyclone Programmable Delay Chain
Programmable Delays
Quartus II Logic Option
Input pin to logic array delay
Decrease input delay to internal cells
Input pin to input register delay
Decrease input delay to input registers
Output pin delay
Increase delay to output pin
相关PDF资料 |
PDF描述 |
|---|---|
| EP1C6T240C6ES | Cyclone FPGA Family Data Sheet |
| EP1C6T240C7ES | Cyclone FPGA Family Data Sheet |
| EP1C6T240C8ES | Cyclone FPGA Family Data Sheet |
| EP1C6T240I6ES | Cyclone FPGA Family Data Sheet |
| EP1C6T240I7ES | Cyclone FPGA Family Data Sheet |
相关代理商/技术参数 |
参数描述 |
|---|---|
| EP1F | 制造商:NEC 制造商全称:NEC 功能描述:HIGH HEAT RESISTIVITY |
| EP1F-B3G1 | 制造商:NEC 制造商全称:NEC 功能描述:HIGH HEAT RESISTIVITY |
| EP1FB3G1S | 制造商:World Products 功能描述:Electromechanical Relay SPDT 25A 12VDC 225Ohm Through Hole |
| EP1F-B3G1T | 制造商:NEC 制造商全称:NEC 功能描述:HIGH HEAT RESISTIVITY |
| EP1F-B3G1TT | 制造商:NEC 制造商全称:NEC 功能描述:HIGH HEAT RESISTIVITY |
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