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| 型号： | EP1K50FC484-2X |
| 英文描述： | Field Programmable Gate Array (FPGA) |
| 中文描述： | 现场可编程门阵列（FPGA） |
| 文件页数： | 54/86页 |
| 文件大小： | 1263K |
| 代理商： | EP1K50FC484-2X |
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58
Altera Corporation
ACEX 1K Programmable Logic Device Family Data Sheet
Notes to tables:
(1)
Microparameters are timing delays contributed by individual architectural elements. These parameters cannot be
measured explicitly.
(2)
Operating conditions: VCCIO = 3.3 V ± 10% for commercial or industrial use in ACEX 1K devices
(3)
Operating conditions: VCCIO = 2.5 V ± 5% for commercial or industrial use in ACEX 1K devices.
(4)
Operating conditions: VCCIO = 2.5 V or 3.3 V.
(5)
Because the RAM in the EAB is self-timed, this parameter can be ignored when the WE signal is registered.
(6)
EAB macroparameters are internal parameters that can simplify predicting the behavior of an EAB at its boundary;
these parameters are calculated by summing selected microparameters.
(7)
These parameters are worst-case values for typical applications. Post-compilation timing simulation and timing
analysis are required to determine actual worst-case performance.
Table 26. Interconnect Timing Microparameters
Symbol
Parameter
Conditions
tDIN2IOE
Delay from dedicated input pin to IOE control input
tDIN2LE
Delay from dedicated input pin to LE or EAB control input
tDIN2DATA
Delay from dedicated input or clock to LE or EAB data
tDCLK2IOE
Delay from dedicated clock pin to IOE clock
tDCLK2LE
Delay from dedicated clock pin to LE or EAB clock
tSAMELAB
Routing delay for an LE driving another LE in the same LAB
tSAMEROW
Routing delay for a row IOE, LE, or EAB driving a row IOE, LE, or EAB in the
same row
tSAMECOLUMN
Routing delay for an LE driving an IOE in the same column
tDIFFROW
Routing delay for a column IOE, LE, or EAB driving an LE or EAB in a different
row
tTWOROWS
Routing delay for a row IOE or EAB driving an LE or EAB in a different row
tLEPERIPH
Routing delay for an LE driving a control signal of an IOE via the peripheral
control bus
tLABCARRY
Routing delay for the carry-out signal of an LE driving the carry-in signal of a
different LE in a different LAB
tLABCASC
Routing delay for the cascade-out signal of an LE driving the cascade-in
signal of a different LE in a different LAB
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相关代理商/技术参数 |
参数描述 |
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| EP1K50FC484-3 | 功能描述:FPGA - 现场可编程门阵列 FPGA - ACEX 1K 360 LABs 249 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| EP1K50FC484-3F | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Field Programmable Gate Array (FPGA) |
| EP1K50FC484-3N | 功能描述:FPGA - 现场可编程门阵列 FPGA - ACEX 1K 360 LABs 249 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| EP1K50FI256-1DX | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Field Programmable Gate Array (FPGA) |
| EP1K50FI256-1F | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Field Programmable Gate Array (FPGA) |
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