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| 型号： | EP1K50QI208-1F |
| 英文描述： | Field Programmable Gate Array (FPGA) |
| 中文描述： | 现场可编程门阵列（FPGA） |
| 文件页数： | 5/86页 |
| 文件大小： | 1263K |
| 代理商： | EP1K50QI208-1F |
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Altera Corporation
13
ACEX 1K Programmable Logic Device Family Data Sheet
Development
13
Tools
If necessary, all EABs in a device can be cascaded to form a single RAM
block. EABs can be cascaded to form RAM blocks of up to 2,048 words
without impacting timing. Altera software automatically combines EABs
to meet a designer’s RAM specifications.
EABs provide flexible options for driving and controlling clock signals.
Different clocks and clock enables can be used for reading and writing to
the EAB. Registers can be independently inserted on the data input, EAB
output, write address, write enable signals, read address, and read enable
signals. The global signals and the EAB local interconnect can drive
write-enable, read-enable, and clock-enable signals. The global signals,
dedicated clock pins, and EAB local interconnect can drive the EAB clock
signals. Because the LEs drive the EAB local interconnect, the LEs can
control write-enable, read-enable, clear, clock, and clock-enable signals.
An EAB is fed by a row interconnect and can drive out to row and column
interconnects. Each EAB output can drive up to two row channels and up
to two column channels; the unused row channel can be driven by other
LEs. This feature increases the routing resources available for EAB
to the EAB, has twice as many channels as other columns in the device.
Logic Array Block
An LAB consists of eight LEs, their associated carry and cascade chains,
LAB control signals, and the LAB local interconnect. The LAB provides
the coarse-grained structure to the ACEX 1K architecture, facilitating
efficient routing with optimum device utilization and high performance.
Figure 7 shows the ACEX 1K LAB.
相关PDF资料 |
PDF描述 |
|---|---|
| EP1K50QI208-1P | Field Programmable Gate Array (FPGA) |
| EP1K50QI208-1X | Field Programmable Gate Array (FPGA) |
| EP1K50QI208-2DX | Single Volatile 32-Tap Digitally Controlled Potentiometer (XDCP™); Temperature Range: -40°C to 85°C; Package: 5-SC-70 T&R |
| EP1K50QI208-2F | Field Programmable Gate Array (FPGA) |
| EP1K50QI208-2P | Field Programmable Gate Array (FPGA) |
相关代理商/技术参数 |
参数描述 |
|---|---|
| EP1K50QI208-1P | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Field Programmable Gate Array (FPGA) |
| EP1K50QI208-1X | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Field Programmable Gate Array (FPGA) |
| EP1K50QI208-2 | 功能描述:FPGA - 现场可编程门阵列 FPGA - ACEX 1K 360 LABs 147 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| EP1K50QI208-2DX | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Field Programmable Gate Array (FPGA) |
| EP1K50QI208-2F | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Field Programmable Gate Array (FPGA) |
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