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| 型号： | EP1K50TI144-1DX |
| 英文描述： | Field Programmable Gate Array (FPGA) |
| 中文描述： | 现场可编程门阵列（FPGA） |
| 文件页数： | 26/86页 |
| 文件大小： | 1263K |
| 代理商： | EP1K50TI144-1DX |
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32
Altera Corporation
ACEX 1K Programmable Logic Device Family Data Sheet
When dedicated inputs drive non-inverted and inverted peripheral clears,
clock enables, and output enables, two signals on the peripheral control
bus will be used.
Table 7 lists the sources for each peripheral control signal and shows how
the output enable, clock enable, clock, and clear signals share
12 peripheral control signals. Table 7 also shows the rows that can drive
global signals.
Signals on the peripheral control bus can also drive the four global signals,
referred to as GLOBAL0 through GLOBAL3. An internally generated signal
can drive a global signal, providing the same low-skew, low-delay
characteristics as a signal driven by an input pin. An LE drives the global
signal by driving a row line that drives the peripheral bus which then
drives the global signal. This feature is ideal for internally generated clear
or clock signals with high fan-out. However, internally driven global
signals offer no advantage over the general-purpose interconnect for
routing data signals.
The chip-wide output enable pin is an active-low pin that can be used to
tri-state all pins on the device. This option can be set in the Altera
software. The built-in I/O pin pull-up resistors (which are active during
configuration) are active when the chip-wide output enable pin is
asserted. The registers in the IOE can also be reset by the chip-wide reset
pin.
Table 7. Peripheral Bus Sources for ACEX Devices
Peripheral Control Signal
EP1K10
EP1K30
EP1K50
EP1K100
OE0
Row A
OE1
Row A
Row B
Row C
OE2
Row B
Row C
Row D
Row E
OE3
Row B
Row D
Row F
Row L
OE4
Row C
Row E
Row H
Row I
OE5
Row C
Row F
Row J
Row K
CLKENA0
/CLK0/GLOBAL0
Row A
Row F
CLKENA1
/OE6/GLOBAL1
Row A
Row B
Row C
Row D
CLKENA2
/CLR0
Row B
Row C
Row E
Row B
CLKENA3
/OE7/GLOBAL2
Row B
Row D
Row G
Row H
CLKENA4
/CLR1
Row C
Row E
Row I
Row J
CLKENA5
/CLK1/GLOBAL3
Row C
Row F
Row J
Row G
相关PDF资料 |
PDF描述 |
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| EP1K50FC256-1DX | Dual LDO with Low Noise, Low IQ, and High PSRR; Temperature Range: -40°C to 85°C; Package: 10-DFN |
| EP1K50FC256-1F | Field Programmable Gate Array (FPGA) |
| EP1K50FC256-1P | Field Programmable Gate Array (FPGA) |
| EP1K50FC256-1X | Field Programmable Gate Array (FPGA) |
| EP1K50FC256-2DX | Field Programmable Gate Array (FPGA) |
相关代理商/技术参数 |
参数描述 |
|---|---|
| EP1K50TI144-1F | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Field Programmable Gate Array (FPGA) |
| EP1K50TI144-1P | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Field Programmable Gate Array (FPGA) |
| EP1K50TI144-1X | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Field Programmable Gate Array (FPGA) |
| EP1K50TI144-2 | 功能描述:FPGA - 现场可编程门阵列 FPGA - ACEX 1K 360 LABs 102 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| EP1K50TI144-2DX | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Field Programmable Gate Array (FPGA) |
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