参数资料
| 型号： | EP1K50TI144-2N |
| 厂商： | Altera |
| 文件页数： | 67/86页 |
| 文件大小： | 0K |
| 描述： | IC ACEX 1K FPGA 50K 144-TQFP |
| 产品培训模块： | Three Reasons to Use FPGA's in Industrial Designs |
| 标准包装： | 180 |
| 系列： | ACEX-1K® |
| LAB/CLB数： | 360 |
| 逻辑元件/单元数： | 2880 |
| RAM 位总计： | 40960 |
| 输入/输出数： | 102 |
| 门数： | 199000 |
| 电源电压： | 2.375 V ~ 2.625 V |
| 安装类型： | 表面贴装 |
| 工作温度： | -40°C ~ 100°C |
| 封装/外壳： | 144-LQFP |
| 供应商设备封装： | 144-TQFP（20x20） |
| 其它名称： | 544-1850 EP1K50TI144-2N-ND |
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Altera Corporation
7
ACEX 1K Programmable Logic Device Family Data Sheet
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The logic array consists of logic array blocks (LABs). Each LAB contains
eight LEs and a local interconnect. An LE consists of a 4-input LUT, a
programmable flipflop, and dedicated signal paths for carry and cascade
functions. The eight LEs can be used to create medium-sized blocks of
logic—such as 8-bit counters, address decoders, or state machines—or
combined across LABs to create larger logic blocks. Each LAB represents
about 96 usable logic gates.
Signal interconnections within ACEX 1K devices (as well as to and from
device pins) are provided by the FastTrack Interconnect routing structure,
which is a series of fast, continuous row and column channels that run the
entire length and width of the device.
Each I/O pin is fed by an I/O element (IOE) located at the end of each row
and column of the FastTrack Interconnect routing structure. Each IOE
contains a bidirectional I/O buffer and a flipflop that can be used as either
an output or input register to feed input, output, or bidirectional signals.
When used with a dedicated clock pin, these registers provide exceptional
performance. As inputs, they provide setup times as low as 1.1 ns and
hold times of 0 ns. As outputs, these registers provide clock-to-output
times as low as 2.5 ns. IOEs provide a variety of features, such as JTAG
BST support, slew-rate control, tri-state buffers, and open-drain outputs.
Figure 1 shows a block diagram of the ACEX 1K device architecture. Each
group of LEs is combined into an LAB; groups of LABs are arranged into
rows and columns. Each row also contains a single EAB. The LABs and
EABs are interconnected by the FastTrack Interconnect routing structure.
IOEs are located at the end of each row and column of the FastTrack
Interconnect routing structure.
相关PDF资料 |
PDF描述 |
|---|---|
| EP1K50TI144-2 | IC ACEX 1K FPGA 50K 144-TQFP |
| A40MX02-1PQ100I | IC FPGA MX SGL CHIP 3K 100-PQFP |
| GSC65DRYI | CONN EDGECARD 130PS DIP .100 SLD |
| GMC65DRYI | CONN EDGECARD 130PS DIP .100 SLD |
| ACM43DTKI | CONN EDGECARD 86POS DIP .156 SLD |
相关代理商/技术参数 |
参数描述 |
|---|---|
| EP1K50TI144-2P | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Field Programmable Gate Array (FPGA) |
| EP1K50TI144-2X | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Field Programmable Gate Array (FPGA) |
| EP1K50TI144-3F | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Field Programmable Gate Array (FPGA) |
| EP1M120 | 制造商:ALTERA 制造商全称:Altera Corporation 功能描述:Programmable Logic Device Family |
| EP1M120F484C5 | 功能描述:FPGA - 现场可编程门阵列 FPGA - MERCURY 480 LABs 303 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
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