参数资料
型号: EP1K50TI144-2N
厂商: Altera
文件页数: 78/86页
文件大小: 0K
描述: IC ACEX 1K FPGA 50K 144-TQFP
产品培训模块: Three Reasons to Use FPGA's in Industrial Designs
标准包装: 180
系列: ACEX-1K®
LAB/CLB数: 360
逻辑元件/单元数: 2880
RAM 位总计: 40960
输入/输出数: 102
门数: 199000
电源电压: 2.375 V ~ 2.625 V
安装类型: 表面贴装
工作温度: -40°C ~ 100°C
封装/外壳: 144-LQFP
供应商设备封装: 144-TQFP(20x20)
其它名称: 544-1850
EP1K50TI144-2N-ND
8
Altera Corporation
ACEX 1K Programmable Logic Device Family Data Sheet
Figure 1. ACEX 1K Device Block Diagram
ACEX 1K devices provide six dedicated inputs that drive the flipflops’
control inputs and ensure the efficient distribution of high-speed, low-
skew (less than 1.0 ns) control signals. These signals use dedicated routing
channels that provide shorter delays and lower skews than the FastTrack
Interconnect routing structure. Four of the dedicated inputs drive four
global signals. These four global signals can also be driven by internal
logic, providing an ideal solution for a clock divider or an internally
generated asynchronous clear signal that clears many registers in the
device.
I/O Element
(IOE)
Logic Array
Block (LAB)
Row
Interconnect
IOE
Local Interconnect
IOE
Logic Element (LE)
Column
Interconnect
IOE
EAB
Logic
Array
IOE
Embedded Array Block (EAB)
Embedded Array
IOE
Logic Array
IOE
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