参数资料
型号: EP20K1000E
厂商: Altera Corporation
英文描述: Programmable Logic Device Family
中文描述: 可编程逻辑器件系列
文件页数: 10/117页
文件大小: 570K
代理商: EP20K1000E
10
Altera Corporation
APEX 20K Programmable Logic Device Family Data Sheet
APEX 20K devices provide two dedicated clock pins and four dedicated
input pins that drive register control inputs. These signals ensure efficient
distribution of high-speed, low-skew control signals. These signals use
dedicated routing channels to provide short delays and low skews. Four
of the dedicated inputs drive four global signals. These four global signals
can also be driven by internal logic, providing an ideal solution for a clock
divider or internally generated asynchronous clear signals with high
fan-out. The dedicated clock pins featured on the APEX 20K devices can
also feed logic. The devices also feature ClockLock and ClockBoost clock
management circuitry. APEX 20KE devices provide two additional
dedicated clock pins, for a total of four dedicated clock pins.
MegaLAB Structure
APEX 20K devices are constructed from a series of MegaLAB
TM
structures. Each MegaLAB structure contains a group of logic array blocks
(LABs), one ESB, and a MegaLAB interconnect, which routes signals
within the MegaLAB structure. The EP20K30E device has 10 LABs,
EP20K60E through EP20K600E devices have 16 LABs, and the
EP20K1000E and EP20K1500E devices have 24 LABs. Signals are routed
between MegaLAB structures and I/O pins via the FastTrack
Interconnect. In addition, edge LABs can be driven by I/O pins through
the local interconnect.
Figure 2
shows the MegaLAB structure.
Figure 2. MegaLAB Structure
ESB
MegaLAB Interconnect
Local
Interconnect
To Adjacent
LAB or IOEs
LABs
LE1
LE2
LE3
LE4
LE5
LE6
LE7
LE8
LE9
LE10
LE1
LE2
LE3
LE4
LE5
LE6
LE7
LE8
LE9
LE10
LE1
LE2
LE3
LE4
LE5
LE6
LE7
LE8
LE9
LE10
相关PDF资料
PDF描述
EP20K100E Programmable Logic Device Family
EP20K1500E Programmable Logic Device Family
EP20K160E Programmable Logic Device Family
EP20K200 Programmable Logic Device Family
EP20K200E Programmable Logic Device Family
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EP20K1000EBC652-1 功能描述:FPGA - 现场可编程门阵列 CPLD - APEX 20K 2560 Macros 488 IO RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256
EP20K1000EBC652-1ES 制造商:未知厂家 制造商全称:未知厂家 功能描述:FPGA
EP20K1000EBC652-1X 功能描述:FPGA - 现场可编程门阵列 CPLD - APEX 20K 2560 Macros 488 IO RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256
EP20K1000EBC652-2 功能描述:FPGA - 现场可编程门阵列 CPLD - APEX 20K 2560 Macros 488 IO RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256
EP20K1000EBC652-2ES 制造商:未知厂家 制造商全称:未知厂家 功能描述:FPGA