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参数资料
| 型号： | EP20K100BC196-3 |
| 厂商： | ALTERA CORP |
| 元件分类： | PLD |
| 英文描述： | LOADABLE PLD, PBGA196 |
| 文件页数： | 54/68页 |
| 文件大小： | 975K |
| 代理商： | EP20K100BC196-3 |
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58
4317K–AVR–03/2013
AT90PWM2/3/2B/3B
Notes:
1. When the BOOTRST Fuse is programmed, the device will jump to the Boot Loader address at
2. When the IVSEL bit in MCUCR is set, Interrupt Vectors will be moved to the start of the Boot
Flash Section. The address of each Interrupt Vector will then be the address in this table
added to the start address of the Boot Flash Section.
Table 10-2 shows reset and Interrupt Vectors placement for the various combinations of
BOOTRST and IVSEL settings. If the program never enables an interrupt source, the Interrupt
Vectors are not used, and regular program code can be placed at these locations. This is also
the case if the Reset Vector is in the Application section while the Interrupt Vectors are in the
Boot section or vice versa.
Note:
1. The Boot Reset Address is shown in Table 24-6 on page 278. For the BOOTRST Fuse “1”
means unprogrammed while “0” means programmed.
The most typical and general program setup for the Reset and Interrupt Vector Addresses in
AT90PWM2/2B/3/3B is:
Address
Labels Code
Comments
0x000
rjmp
RESET
; Reset Handler
0x001
rjmp
PSC2_CAPT
; PSC2 Capture event Handler
0x002
rjmp
PSC2_EC
; PSC2 End Cycle Handler
0x003
rjmp
PSC1_CAPT
; PSC1 Capture event Handler
0x004
rjmp
PSC1_EC
; PSC1 End Cycle Handler
0x005
rjmp
PSC0_CAPT
; PSC0 Capture event Handler
0x006
rjmp
PSC0_EC
; PSC0 End Cycle Handler
0x007
rjmp
ANA_COMP_0
; Analog Comparator 0 Handler
0x008
rjmp
ANA_COMP_1
; Analog Comparator 1 Handler
0x009
rjmp
ANA_COMP_2
; Analog Comparator 2 Handler
0x00A
rjmp
EXT_INT0
; IRQ0 Handler
0x00B
rjmp
TIM1_CAPT
; Timer1 Capture Handler
0x00C
rjmp
TIM1_COMPA
; Timer1 Compare A Handler
0x00D
rjmp
TIM1_COMPB
; Timer1 Compare B Handler
0x00F
rjmp
TIM1_OVF
; Timer1 Overflow Handler
29
0x001C
INT3
External Interrupt Request 3
30
0x001D
31
0x001E
32
0x001F
SPM READY
Store Program Memory Ready
Table 10-2.
Reset and Interrupt Vectors Placement in AT90PWM2/2B/3/3B
BOOTRST
IVSEL
Reset Address
Interrupt Vectors Start Address
1
0
0x000
0x001
1
0x000
Boot Reset Address + 0x001
0
Boot Reset Address
0x001
0
1
Boot Reset Address
Boot Reset Address + 0x001
Table 10-1.
Reset and Interrupt Vectors
Vector
No.
Program
Address
Source
Interrupt Definition
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PDF描述 |
|---|---|
| EP20K100BI196-1 | LOADABLE PLD, PBGA196 |
| EP20K100BI196-2 | LOADABLE PLD, PBGA196 |
| EP20K100BI196-3 | LOADABLE PLD, PBGA196 |
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相关代理商/技术参数 |
参数描述 |
|---|---|
| EP20K100BC356-1 | 功能描述:FPGA - 现场可编程门阵列 CPLD - APEX 20K 416 Macro 252 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| EP20K100BC356-1ES | 制造商:未知厂家 制造商全称:未知厂家 功能描述:FPGA |
| EP20K100BC356-1V | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| EP20K100BC356-2 | 功能描述:FPGA - 现场可编程门阵列 CPLD - APEX 20K 416 Macro 252 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| EP20K100BC356-2ES | 制造商:未知厂家 制造商全称:未知厂家 功能描述:FPGA |
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