参数资料
型号: EP20K100EFC324-2
厂商: Altera
文件页数: 50/117页
文件大小: 0K
描述: IC APEX 20KE FPGA 100K 324-FBGA
产品培训模块: Three Reasons to Use FPGA's in Industrial Designs
标准包装: 84
系列: APEX-20K®
LAB/CLB数: 416
逻辑元件/单元数: 4160
RAM 位总计: 53248
输入/输出数: 246
门数: 263000
电源电压: 1.71 V ~ 1.89 V
安装类型: 表面贴装
工作温度: 0°C ~ 85°C
封装/外壳: 324-BGA
供应商设备封装: 324-FBGA(19x19)
38
Altera Corporation
APEX 20K Programmable Logic Device Family Data Sheet
Table 10 describes the APEX 20K programmable delays and their logic
options in the Quartus II software.
The Quartus II software compiler can program these delays automatically
to minimize setup time while providing a zero hold time. Figure 25 shows
how fast bidirectional I/Os are implemented in APEX 20K devices.
The register in the APEX 20K IOE can be programmed to power-up high
or low after configuration is complete. If it is programmed to power-up
low, an asynchronous clear can control the register. If it is programmed to
power-up high, the register cannot be asynchronously cleared or preset.
This feature is useful for cases where the APEX 20K device controls an
active-low input or another device; it prevents inadvertent activation of
the input upon power-up.
Table 10. APEX 20K Programmable Delay Chains
Programmable Delays
Quartus II Logic Option
Input pin to core delay
Decrease input delay to internal cells
Input pin to input register delay
Decrease input delay to input register
Core to output register delay
Decrease input delay to output register
Output register tCO delay
Increase delay to output pin
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EP20K100EFC3242XN 制造商:Altera Corporation 功能描述:FPGA APEX 20K Family 100K Gates 4160 Cells 250MHz CMOS Technology 1.8V 324-Pin FBGA
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