参数资料
型号: EP20K100EFC784-1
厂商: ALTERA CORP
元件分类: PLD
英文描述: LOADABLE PLD, PBGA784
文件页数: 42/65页
文件大小: 781K
代理商: EP20K100EFC784-1
Altera Corporation
69
Preliminary Information
APEX 20K Programmable Logic Device Family Data Sheet
Figure 31. Specications for the Incoming & Generated Clocks
The tI parameter refers to the nominal input clock period; the tO parameter refers to the
nominal output clock period.
Table 10 summarizes the ClockLock and ClockBoost parameters for
APEX 20K devices. Specifications for APEX 20KE devices will be released
in a future data sheet.
Input
Clock
ClockLock
Generated
Clock
f CLK1 f CLK2
f CLK4
t INDUTY
t I + t CLKDEV
t R
t F
t O
t I + t INCLKSTB
t O
tO
t JITTER
tO + t JITTER
tOUTDUTY
,
Table 10. ClockLock & ClockBoost Parameters
Symbol
Parameter
Min
Typ
Max
Unit
tR
Input rise time
5
ns
tF
Input fall time
5
ns
tINDUTY
Input duty cycle
40
60
%
fCLK1
Input clock frequency (ClockBoost clock multiplication factor equals 1)
25
133
MHz
fCLK2
Input clock frequency (ClockBoost clock multiplication factor equals 2)
20
66
MHz
fCLKDEV
Input deviation from user specification in the Quartus software (ClockBoost clock
multiplication factor equals 1)
25,000
PPM
fCLK4
Input clock frequency (ClockBoost clock multiplication factor equals 4)
15
33
MHz
tINCLKSTB
Input clock stability (measured between adjacent clocks)
100
ps
tLOCK
Time required for ClockLock or ClockBoost to acquire lock
10
s
tJITTER
Jitter on ClockLock or ClockBoost-generated clock
250
ps
tOUTDUTY
Duty cycle for ClockLock or ClockBoost-generated clock
40
50
60
%
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