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| 型号： | EP20K100EFI784-2 |
| 厂商： | ALTERA CORP |
| 元件分类： | PLD |
| 英文描述： | LOADABLE PLD, PBGA784 |
| 文件页数： | 37/65页 |
| 文件大小： | 781K |
| 代理商： | EP20K100EFI784-2 |
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64
Altera Corporation
APEX 20K Programmable Logic Device Family Data Sheet
Preliminary Information
Figure 28. Column IOE Connection to the Interconnect
Advanced I/O Standard Support
The APEX 20KE IOE supports the following I/O standards: LVTTL,
LVCMOS, 1.8-V I/O, 2.5-V I/O, 3.3-V PCI, 3.3-V AGP, LVDS, GTL+,
SSTL-3 Class I and II, SSTL-2 Class I and II, and HSTL Class I, II, and III.
The APEX 20KE device contains eight I/O blocks. All blocks support all
standards except LVDS. In addition, one block supports LVDS inputs, and
another block supports LVDS outputs. Each I/O block has its own VCCIO
pins. A single device can support 1.8-V, 2.5-V, and 3.3-V interfaces; each
block can support a different standard independently. Each block can also
use a separate VREF level, so that each block can support any of the
terminated standards (such as SSTL-3) independently. Within a block,
any one of the terminated standards can be supported. EP20K300E and
larger APEX 20KE devices support the LVDS interface.
When LVDS signals are used within a block, other I/O standards should
not be used within the same block to avoid degrading the high-
performance LVDS signal. An exception can be made for the ClockLock
LOCK
signal, which does not toggle during normal operation. Figure 29
shows the arrangement of the APEX 20KE I/O blocks.
Row Interconnect
Column Interconnect
Each IOE can drive column interconnect. In APEX 20KE devices,
IOEs can also drive FastRow and column interconnect. Each IOE data
and OE signal is driven by local interconnect.
Any LE or ESB can drive
a column pin through a
row, column, and MegaLAB
interconnect.
IOE
LAB
An LE or ESB can drive a
pin through a local
interconnect for faster
clock-to-output times.
MegaLAB Interconnect
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相关代理商/技术参数 |
参数描述 |
|---|---|
| EP20K100EQC208-1 | 功能描述:FPGA - 现场可编程门阵列 CPLD - APEX 20K 416 Macro 151 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| EP20K100EQC208-1ES | 制造商:未知厂家 制造商全称:未知厂家 功能描述:FPGA |
| EP20K100EQC208-1X | 功能描述:FPGA - 现场可编程门阵列 CPLD - APEX 20K 416 Macro 151 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| EP20K100EQC208-2 | 功能描述:FPGA - 现场可编程门阵列 CPLD - APEX 20K 416 Macro 151 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| EP20K100EQC208-2ES | 制造商:未知厂家 制造商全称:未知厂家 功能描述:FPGA |
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