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参数资料
| 型号： | EP20K100ERC240-3ES |
| 元件分类： | 数字电位计 |
| 英文描述： | Single Digitally Controlled Potentiometer (XDCP™); Temperature Range: -40°C to 85°C; Package: 8-TDFN |
| 中文描述： | FPGA的 |
| 文件页数： | 21/114页 |
| 文件大小： | 1623K |
| 代理商： | EP20K100ERC240-3ES |
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14
Altera Corporation
APEX 20K Programmable Logic Device Family Data Sheet
Each LE has two outputs that drive the local, MegaLAB, or FastTrack
Interconnect routing structure. Each output can be driven independently
by the LUT’s or register’s output. For example, the LUT can drive one
output while the register drives the other output. This feature, called
register packing, improves device utilization because the register and the
LUT can be used for unrelated functions. The LE can also drive out
registered and unregistered versions of the LUT output.
The APEX 20K architecture provides two types of dedicated high-speed
data paths that connect adjacent LEs without using local interconnect
paths: carry chains and cascade chains. A carry chain supports high-speed
arithmetic functions such as counters and adders, while a cascade chain
implements wide-input functions such as equality comparators with
minimum delay. Carry and cascade chains connect LEs 1 through 10 in an
LAB and all LABs in the same MegaLAB structure.
Carry Chain
The carry chain provides a very fast carry-forward function between LEs.
The carry-in signal from a lower-order bit drives forward into the higher-
order bit via the carry chain, and feeds into both the LUT and the next
portion of the carry chain. This feature allows the APEX 20K architecture
to implement high-speed counters, adders, and comparators of arbitrary
width. Carry chain logic can be created automatically by the Quartus II
software Compiler during design processing, or manually by the designer
during design entry. Parameterized functions such as library of
parameterized modules (LPM) and DesignWare functions automatically
take advantage of carry chains for the appropriate functions.
The Quartus II software Compiler creates carry chains longer than ten LEs
by linking LABs together automatically. For enhanced fitting, a long carry
chain skips alternate LABs in a MegaLAB structure. A carry chain longer
than one LAB skips either from an even-numbered LAB to the next even-
numbered LAB, or from an odd-numbered LAB to the next odd-
numbered LAB. For example, the last LE of the first LAB in the upper-left
MegaLAB structure carries to the first LE of the third LAB in the
MegaLAB structure.
Figure 6 shows how an n-bit full adder can be implemented in n + 1 LEs
with the carry chain. One portion of the LUT generates the sum of two bits
using the input signals and the carry-in signal; the sum is routed to the
output of the LE. The register can be bypassed for simple adders or used
for accumulator functions. Another portion of the LUT and the carry chain
logic generates the carry-out signal, which is routed directly to the carry-
in signal of the next-higher-order bit. The final carry-out signal is routed
to an LE, where it is driven onto the local, MegaLAB, or FastTrack
Interconnect routing structures.
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相关代理商/技术参数 |
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| EP20K100ERI208-1ES | 制造商:未知厂家 制造商全称:未知厂家 功能描述:FPGA |
| EP20K100ERI208-2ES | 制造商:未知厂家 制造商全称:未知厂家 功能描述:FPGA |
| EP20K100ERI208-3ES | 制造商:未知厂家 制造商全称:未知厂家 功能描述:FPGA |
| EP20K100ERI240-1ES | 制造商:未知厂家 制造商全称:未知厂家 功能描述:FPGA |
| EP20K100ERI240-2ES | 制造商:未知厂家 制造商全称:未知厂家 功能描述:FPGA |
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