参数资料
型号: EP20K30ETI144-1ES
英文描述: FPGA
中文描述: FPGA的
文件页数: 1/114页
文件大小: 1623K
代理商: EP20K30ETI144-1ES
Altera Corporation
1
APEX 20K
Programmable Logic
Device Family
May 2001, ver. 3.7
Data Sheet
A-DS-APEX20K-03.7
Features...
s
Industry’s first programmable logic device (PLD) incorporating
system-on-a-programmable-chip (SOPC) integration
–MultiCoreTM architecture integrating look-up table (LUT) logic,
product-term logic, and embedded memory
LUT logic used for register-intensive functions
Embedded system block (ESB) used to implement memory
functions, including first-in first-out (FIFO) buffers, dual-port
RAM, and content-addressable memory (CAM)
ESB implementation of product-term logic used for
combinatorial-intensive functions
s
High density
30,000 to 1.5 million typical gates (see Tables 1 and 2)
Up to 51,840 logic elements (LEs)
Up to 442,368 RAM bits that can be used without reducing
available logic
Up to 3,456 product-term-based macrocells
Table 1. APEX 20K Device Features
Feature
EP20K30E
EP20K60E
EP20K100
EP20K100E
EP20K160E
EP20K200
EP20K200E
Maximum
system
gates
113,000
162,000
263,000
404,000
526,000
Typical
gates
30,000
60,000
100,000
160,000
200,000
LEs
1,200
2,560
4,160
6,400
8,320
ESBs
12
16
26
40
52
Maximum
RAM bits
24,576
32,768
53,248
81,920
106,496
Maximum
macrocells
192
256
416
640
832
Maximum
user I/O
pins
128
196
252
246
316
382
376
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EP20K30ETI144-2ES 制造商:未知厂家 制造商全称:未知厂家 功能描述:FPGA
EP20K30ETI144-3ES 制造商:未知厂家 制造商全称:未知厂家 功能描述:FPGA
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EP20K400BC652-1 功能描述:FPGA - 现场可编程门阵列 CPLD - APEX 20K 1664 Macros 502 IO RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256
EP20K400BC652-1ES 制造商:未知厂家 制造商全称:未知厂家 功能描述:FPGA