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| 型号： | EP20K30ETI144-1ES |
| 英文描述： | FPGA |
| 中文描述： | FPGA的 |
| 文件页数： | 44/114页 |
| 文件大小： | 1623K |
| 代理商： | EP20K30ETI144-1ES |
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Altera Corporation
35
APEX 20K Programmable Logic Device Family Data Sheet
Figure 23. APEX 20KE CAM Block Diagram
CAM can be used in any application requiring high-speed searches, such
as networking, communications, data compression, and cache
management.
The APEX 20KE on-chip CAM provides faster system performance than
traditional discrete CAM. Integrating CAM and logic into the APEX 20KE
device eliminates off-chip and on-chip delays, improving system
performance.
When in CAM mode, the ESB implements 32-word, 32-bit CAM. Wider or
deeper CAM can be implemented by combining multiple CAMs with
some ancillary logic implemented in LEs. The Quartus II software
combines ESBs and LEs automatically to create larger CAMs.
CAM supports writing “don’t care” bits into words of the memory. The
“don’t-care” bit can be used as a mask for CAM comparisons; any bit set
to “don’t-care” has no effect on matches.
The output of the CAM can be encoded or unencoded. When encoded, the
ESB outputs an encoded address of the data’s location. For instance, if the
data is located in address 12, the ESB output is 12. When unencoded, the
ESB uses its 16 outputs to show the location of the data over two clock
cycles. In this case, if the data is located in address 12, the 12th output line
goes high. When using unencoded outputs, two clock cycles are required
to read the output because a 16-bit output bus is used to show the status
of 32 words.
The encoded output is better suited for designs that ensure duplicate data
is not written into the CAM. If duplicate data is written into two locations,
the CAM’s output will be incorrect. If the CAM may contain duplicate
data, the unencoded output is a better solution; CAM with unencoded
outputs can distinguish multiple data locations.
CAM can be pre-loaded with data during configuration, or it can be
written during system operation. In most cases, two clock cycles are
required to write each word into CAM. When “don’t-care” bits are used,
a third clock cycle is required.
wraddress[]
data[]
wren
inclock
inclocken
inaclr
data_address[]
match
outclock
outclocken
outaclr
相关PDF资料 |
PDF描述 |
|---|---|
| EP20K30ETI144-2ES | FPGA |
| EP20K30ETI144-3ES | FPGA |
| EP20K400BC652-1 | Field Programmable Gate Array (FPGA) |
| EP20K400BC652-1ES | FPGA |
| EP20K400BC652-2 | Field Programmable Gate Array (FPGA) |
相关代理商/技术参数 |
参数描述 |
|---|---|
| EP20K30ETI144-2ES | 制造商:未知厂家 制造商全称:未知厂家 功能描述:FPGA |
| EP20K30ETI144-3ES | 制造商:未知厂家 制造商全称:未知厂家 功能描述:FPGA |
| EP20K400 | 制造商:ALTERA 制造商全称:Altera Corporation 功能描述:Programmable Logic Device Family |
| EP20K400BC652-1 | 功能描述:FPGA - 现场可编程门阵列 CPLD - APEX 20K 1664 Macros 502 IO RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| EP20K400BC652-1ES | 制造商:未知厂家 制造商全称:未知厂家 功能描述:FPGA |
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