参数资料
型号: EP2AGX125DF25C5N
厂商: Altera
文件页数: 59/90页
文件大小: 0K
描述: IC ARRIA II GX FPGA 125K 572FBGA
产品培训模块: Three Reasons to Use FPGA's in Industrial Designs
标准包装: 5
系列: Arria II GX
LAB/CLB数: 4964
逻辑元件/单元数: 118143
RAM 位总计: 8315904
输入/输出数: 260
电源电压: 0.87 V ~ 0.93 V
安装类型: 表面贴装
工作温度: 0°C ~ 85°C
封装/外壳: 572-FBGA
供应商设备封装: 572-FBGA
1–54
Chapter 1: Device Datasheet for Arria II Devices
Switching Characteristics
December 2013
Altera Corporation
fOUT
Output frequency for internal global or regional clock
(–4 Speed Grade)
500
MHz
Output frequency for internal global or regional clock
(–5 Speed Grade)
500
MHz
Output frequency for internal global or regional clock
(–6 Speed Grade)
400
MHz
fOUT_EXT
Output frequency for external clock output (–4 Speed Grade)
670 (5)
MHz
Output frequency for external clock output (–5 Speed Grade)
622 (5)
MHz
Output frequency for external clock output (–6 Speed Grade)
500 (5)
MHz
tOUTDUTY
Duty cycle for external clock output (when set to 50%)
45
50
55
%
tOUTPJ_DC
Dedicated clock output period jitter (fOUT 100 MHz)
300
ps (p–p)
Dedicated clock output period jitter (fOUT 100 MHz)
30
mUI (p–p)
tOUTCCJ_DC
Dedicated clock output cycle-to-cycle jitter (fOUT 100 MHz)
300
ps (p–p)
Dedicated clock output cycle-to-cycle jitter (fOUT 100 MHz)
30
mUI (p–p)
fOUTPJ_IO
Regular I/O clock output period jitter (fOUT 100 MHz)
650
ps (p–p)
Regular I/O clock output period jitter (fOUT 100 MHz)
65
mUI (p–p)
fOUTCCJ_IO
Regular I/O clock output cycle-to-cycle jitter (fOUT 100 MHz)
650
ps (p–p)
Regular I/O clock output cycle-to-cycle jitter (fOUT 100 MHz)
65
mUI (p–p)
tCONFIGPLL
Time required to reconfigure PLL scan chains
3.5
SCANCLK
cycles
tCONFIGPHASE Time required to reconfigure phase shift
1
SCANCLK
cycles
fSCANCLK
SCANCLK frequency
100
MHz
tLOCK
Time required to lock from end of device configuration
1
ms
tDLOCK
Time required to lock dynamically (after switchover or
reconfiguring any non-post-scale counters/delays)
——
1
ms
fCL B W
PLL closed-loop low bandwidth
0.3
MHz
PLL closed-loop medium bandwidth
1.5
MHz
PLL closed-loop high bandwidth
4
MHz
tPLL_PSERR
Accuracy of PLL phase shift
±50
ps
tARESET
Minimum pulse width on areset signal
10
ns
Table 1–44. PLL Specifications for Arria II GX Devices (Part 2 of 3)
Symbol
Description
Min
Typ
Max
Unit
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EP2AGX125DF25C5NES 制造商:Altera Corporation 功能描述:IC ARRIA II GX FPGA 572FBGA 制造商:Altera Corporation 功能描述:IC FPGA 260 I/O 572FBGA
EP2AGX125DF25C6 功能描述:FPGA - 现场可编程门阵列 FPGA - Arria II GX 4964 LABs 260 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256
EP2AGX125DF25C6N 功能描述:FPGA - 现场可编程门阵列 FPGA - Arria II GX 4964 LABs 260 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256
EP2AGX125DF25C6NES 制造商:Altera Corporation 功能描述:FPGA Arria
EP2AGX125DF25I3 功能描述:IC ARRIA II GX FPGA 125K 572FBGA RoHS:否 类别:集成电路 (IC) >> 嵌入式 - FPGA(现场可编程门阵列) 系列:Arria II GX 产品变化通告:XC4000(E,L) Discontinuation 01/April/2002 标准包装:24 系列:XC4000E/X LAB/CLB数:100 逻辑元件/单元数:238 RAM 位总计:3200 输入/输出数:80 门数:3000 电源电压:4.5 V ~ 5.5 V 安装类型:表面贴装 工作温度:-40°C ~ 100°C 封装/外壳:120-BCBGA 供应商设备封装:120-CPGA(34.55x34.55)