参数资料
| 型号： | EP2AGX260FF35C4 |
| 厂商： | Altera |
| 文件页数： | 60/90页 |
| 文件大小： | 0K |
| 描述： | IC ARRIA II GX 260K 1152FBGA |
| 产品培训模块： | Three Reasons to Use FPGA's in Industrial Designs |
| 标准包装： | 3 |
| 系列： | Arria II GX |
| LAB/CLB数： | 10260 |
| 逻辑元件/单元数： | 244188 |
| RAM 位总计： | 12038144 |
| 输入/输出数： | 612 |
| 电源电压： | 0.87 V ~ 0.93 V |
| 安装类型： | 表面贴装 |
| 工作温度： | 0°C ~ 85°C |
| 封装/外壳： | 1152-BBGA |
| 供应商设备封装： | 1152-FBGA（27x27） |
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Chapter 1: Device Datasheet for Arria II Devices
1–55
Switching Characteristics
December 2013
Altera Corporation
Table 1–45 lists the PLL specifications for Arria II GZ devices when operating in both
the commercial junction temperature range (0° to 85°C) and the industrial junction
temperature range (-40° to 100°C).
tCASC_
OUTJITTER_
PERIOD_
DEDCLK
Period Jitter for dedicated clock output in cascaded PLLs
(FOUT
100 MHz)
—
425
ps (p-p)
Period Jitter for dedicated clock output in cascaded PLLs
(FOUT
100 MHz)
—
42.5
mUI (p-p)
Notes to Table 1–44:
(1) fIN is limited by the I/O fMAX.
(2) The VCO frequency reported by the Quartus II software in the PLL summary section of the compilation report takes into consideration the VCO
post-scale counter K value. Therefore, if the counter K has a value of 2, the frequency reported can be lower than the fVCO specification.
(3) A high-input jitter directly affects the PLL output jitter. To have low PLL output clock jitter, you must provide a clean-clock source, which is
less than 200 ps.
(4) FREF is fIN/N when N = 1.
(5) This specification is limited by the lower of the two: I/O fMAX or fOUT of the PLL.
(6) Peak-to-peak jitter with a probability level of 10–12 (14 sigma, 99.99999999974404% confidence level). The output jitter specification applies
to the intrinsic jitter of the PLL, when an input jitter of 30 ps is applied. The external memory interface clock output jitter specifications use a
different measurement method and are available in Table 1–62 on page 1–70.
(7) The cascaded PLL specification is only applicable with the following condition:
a. Upstream PLL: 0.59 Mhz
Upstream PLL BW < 1 MHz
b. Downstream PLL: Downstream PLL BW > 2 MHz
Table 1–44. PLL Specifications for Arria II GX Devices (Part 3 of 3)
Symbol
Description
Min
Typ
Max
Unit
Table 1–45. PLL Specifications for Arria II GZ Devices (Part 1 of 2)
Symbol
Parameter
Min
Typ
Max
Unit
fIN
Input clock frequency (–3 speed grade)
5
—
717 (1)
MHz
Input clock frequency (–4 speed grade)
5
—
717 (1)
MHz
fINPFD
Input frequency to the PFD
5
—
325
MHz
fVCO
PLL VCO operating range (–3 speed grade)
600
—
1,300
MHz
PLL VCO operating range (–4 speed grade)
600
—
1,300
MHz
tEINDUTY
Input clock or external feedback clock input duty cycle
40
—
60
%
fOUT
Output frequency for internal global or regional clock
(–3 speed grade)
—
700 (2)
MHz
Output frequency for internal global or regional clock
(–4 speed grade)
—
500 (2)
MHz
fOUT_EXT
Output frequency for external clock output (–3 speed grade)
—
717 (2)
MHz
Output frequency for external clock output (–4 speed grade)
—
717 (2)
MHz
tOUTDUTY
Duty cycle for external clock output (when set to 50%)
45
50
55
%
tFCOMP
External feedback clock compensation time
—
10
ns
tCONFIGPLL
Time required to reconfigure scan chain
—
3.5
—
scanclk
cycles
tCONFIGPHASE
Time required to reconfigure phase shift
—
1
—
scanclk
cycles
fSCANCLK
scanclk frequency
—
100
MHz
tLOCK
Time required to lock from end-of-device configuration or
de-assertion of areset
——
1
ms
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相关代理商/技术参数 |
参数描述 |
|---|---|
| EP2AGX260FF35C4N | 功能描述:FPGA - 现场可编程门阵列 FPGA - Arria II GX 10260 LABs 612 IO RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| EP2AGX260FF35C5 | 功能描述:FPGA - 现场可编程门阵列 FPGA - Arria II GX 10260 LABs 612 IO RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| EP2AGX260FF35C5N | 功能描述:FPGA - 现场可编程门阵列 FPGA - Arria II GX 10260 LABs 612 IO RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| EP2AGX260FF35C6 | 功能描述:FPGA - 现场可编程门阵列 FPGA - Arria II GX 10260 LABs 612 IO RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| EP2AGX260FF35C6N | 功能描述:FPGA - 现场可编程门阵列 FPGA - Arria II GX 10260 LABs 612 IO RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
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