参数资料
型号: EP2AGX65CU17C6N
厂商: Altera
文件页数: 31/90页
文件大小: 0K
描述: IC ARRIA II GX FPGA 65K 358UBGA
产品培训模块: Three Reasons to Use FPGA's in Industrial Designs
标准包装: 6
系列: Arria II GX
LAB/CLB数: 2530
逻辑元件/单元数: 60214
RAM 位总计: 5371904
输入/输出数: 156
电源电压: 0.87 V ~ 0.93 V
安装类型: 表面贴装
工作温度: 0°C ~ 85°C
封装/外壳: 358-UBGA
供应商设备封装: 358-UBGA
Chapter 1: Device Datasheet for Arria II Devices
1–29
Switching Characteristics
December 2013
Altera Corporation
Transceiver Clocks
Calibration block clock
frequency (cal_blk_clk)
10
125
10
125
MHz
fixedclk
clock frequency
PCIe Receiver
Detect
125
125
MHz
reconfig_clk
clock
frequency
Dynamic
reconfiguration
clock frequency
2.5/
37.5
—50
2.5/
37.5
—50
MHz
Delta time between
reconfig_clks
——
2
2
ms
Transceiver block minimum
power-down
(gxb_powerdown) pulse
width
—1
1
s
Receiver
Supported I/O Standards
1.4-V PCML, 1.5-V PCML, 2.5-V PCML, LVPECL, and LVDS
600
6375
600
3750
Mbps
Absolute VMAX for a receiver
pin (6)
——
1.6
1.6
V
Operational VMAX for a
receiver pin
——
1.5
1.5
V
Absolute VMIN for a receiver
pin
-0.4
-0.4
V
Maximum peak-to-peak
differential input voltage VID
(diff p-p) before device
configuration
——
1.6
1.6
V
Maximum peak-to-peak
differential input voltage VID
(diff p-p) after device
configuration
VICM = 0.82 V
setting
2.7
2.7
V
VICM =1.1 V setting
1.6
1.6
V
Minimum differential eye
opening at receiver serial
input pins (8)
Data Rate =
600 Mbps to
5 Gbps
Equalization = 0
DC gain = 0 dB
100
165
mV
Data Rate > 5 Gbps
Equalization = 0
DC gain = 0 dB
165
165
mV
VICM
VICM = 0.82 V
setting
820 ± 10%
mV
VICM = 1.1 V setting
1100 ± 10%
mV
Table 1–35. Transceiver Specifications for Arria II GZ Devices (Part 2 of 5)
Symbol/
Description
Conditions
–C3 and –I3 (1)
–C4 and –I4
Unit
Min
Typ
Max
Min
Typ
Max
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