参数资料
型号: EP2AGX65DF25I5N
厂商: Altera
文件页数: 72/90页
文件大小: 0K
描述: IC ARRIA II GX FPGA 65K 572FBGA
产品培训模块: Three Reasons to Use FPGA's in Industrial Designs
标准包装: 5
系列: Arria II GX
LAB/CLB数: 2530
逻辑元件/单元数: 60214
RAM 位总计: 5371904
输入/输出数: 252
电源电压: 0.87 V ~ 0.93 V
安装类型: 表面贴装
工作温度: -40°C ~ 100°C
封装/外壳: 572-FBGA
供应商设备封装: 572-FBGA
1–66
Chapter 1: Device Datasheet for Arria II Devices
Switching Characteristics
December 2013
Altera Corporation
Table 1–55 lists DPA lock time specifications for Arria II GX and GZ devices.
tRISE & tFALL
True differential I/O
standards
200—
—200
ps
Emulated differential
I/O standards with
three external output
resistor networks
250—
—300
ps
Emulated differential
I/O standards with
one external output
resistor
500—
—500
ps
TCCS
True LVDS
100
100
ps
Emulated
LVDS_E_3R
250—
—250
ps
Receiver
True differential I/O
standards - fHSDRDPA
(data rate)
SERDES factor
J = 3 to 10
150
1250
150
1250
Mbps
fHSDR (data rate)
SERDES factor
J = 3 to 10
Mbps
SERDES factor J = 2,
uses DDR registers
Mbps
SERDES factor J = 1,
uses an SDR register
Mbps
DPA run length
DPA mode
10000
10000
UI
Soft-CDR PPM
tolerance
Soft-CDR mode
300
300
± PPM
Sampling Window
(SW)
Non-DPA mode
300
300
ps
Notes to Table 1–54:
(1) When J = 3 to 10, use the SERDES block.
(2) When J = 1 or 2, bypass the SERDES block.
(3) Clock Boost Factor (W) is the ratio between input data rate to the input clock rate.
(4) The minimum specification depends on the clock source (for example, the PLL and clock pin) and the clock routing resource (global, regional,
or local) that you use. The I/O differential buffer and input register do not have a minimum toggle rate.
(5) You must calculate the leftover timing margin in the receiver by performing link timing closure analysis. You must consider the board skew
margin, transmitter channel-to-channel skew, and receiver sampling margin to determine leftover timing margin.
(6) You can estimate the achievable maximum data rate for non-DPA mode by performing link timing closure analysis. You must consider the board
skew margin, transmitter delay margin, and the receiver sampling margin to determine the maximum data rate supported.
(7) This is achieved by using the LVDS and DPA clock network.
(8) If the receiver with DPA enabled and transmitter are using shared PLLs, the minimum data rate is 150 Mbps.
(9) This only applies to DPA and soft-CDR modes.
(10) This only applies to LVDS source synchronous mode.
Table 1–54. High-Speed I/O Specifications for Arria II GZ Devices (Note 1), (2), (10) (Part 3 of 3)
Symbol
Conditions
C3, I3
C4, I4
Unit
Min
Typ
Max
Min
Typ
Max
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