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| 型号： | EP2AGX65DF29C4N |
| 厂商： | Altera |
| 文件页数： | 29/90页 |
| 文件大小： | 0K |
| 描述： | IC ARRIA II GX FPGA 65K 780FBGA |
| 产品培训模块： | Three Reasons to Use FPGA's in Industrial Designs |
| 标准包装： | 4 |
| 系列： | Arria II GX |
| LAB/CLB数： | 2530 |
| 逻辑元件/单元数： | 60214 |
| RAM 位总计： | 5371904 |
| 输入/输出数： | 364 |
| 电源电压： | 0.87 V ~ 0.93 V |
| 安装类型： | 表面贴装 |
| 工作温度： | 0°C ~ 85°C |
| 封装/外壳： | 780-BBGA |
| 供应商设备封装： | 780-FBGA（29x29） |
| 其它名称： | 544-2703 |
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Ch
ap
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r
1:
De
vice
Da
ta
sh
e
tfo
r
Arria
II
De
vice
s
1–2
7
Switc
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ing
C
h
ar
acter
istics
Dec
ember
2013
Alte
ra
Cor
p
oration
A
Digital reset
pulse width
—
Minimum is 2 parallel clock cycles
Notes to Table 1–34:
(1) For AC-coupled links, the on-chip biasing circuit is switched off before and during configuration. Ensure that input specifications are not violated during this period.
(2) The rise/fall time is specified from 20% to 80%.
(3) To calculate the REFCLK rms phase jitter requirement at reference clock frequencies other than 100 MHz, use the following formula:
REFCLK rms phase jitter at f (MHz) = REFCLK rms phase jitter at 100 MHz * 100/f.
(4) The minimum reconfig_clk frequency is 2.5 MHz if the transceiver channel is configured in Transmitter only mode. The minimum reconfig_clk frequency is 37.5 MHz if the transceiver channel is
configured in Receiver only or Receiver and Transmitter mode. For more information, refer to AN 558: Implementing Dynamic Reconfiguration in Arria II Devices.
(5) If your design uses more than one dynamic reconfiguration controller instances (altgx_reconfig) to control the transceiver channels (altgx) physically located on the same side of the device, and if
you use different reconfig_clk sources for these altgx_reconfig instances, the delta time between any two of these reconfig_clk sources becoming stable must not exceed the maximum
specification listed.
(6) The device cannot tolerate prolonged operation at this absolute maximum.
(7) You must use the 1.1-V RX VICM setting if the input serial data standard is LVDS and the link is DC-coupled.
(8) The rate matcher supports only up to ±300 parts per million (ppm).
(9) Time taken to rx_pll_locked goes high from rx_analogreset de-assertion. Refer to Figure 1–1.
(10) The time in which the CDR must be kept in lock-to-reference mode after rx_pll_locked goes high and before rx_locktodata is asserted in manual mode. Refer to Figure 1–1.
(11) The time taken to recover valid data after the rx_locktodata signal is asserted in manual mode. Refer to Figure 1–1.
(12) The time taken to recover valid data after the rx_freqlocked signal goes high in automatic mode. Refer to Figure 1–2.
(13) To support data rates lower than the minimum specification through oversampling, use the CDR in LTR mode only.
Table 1–34. Transceiver Specifications for Arria II GX Devices (Note 1) (Part 7 of 7)
Symbol/
Description
Condition
I3
C4
C5 and I5
C6
Unit
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
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相关代理商/技术参数 |
参数描述 |
|---|---|
| EP2AGX65DF29C5 | 功能描述:FPGA - 现场可编程门阵列 FPGA - Arria II GX 2530 LABs 364 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| EP2AGX65DF29C5N | 功能描述:FPGA - 现场可编程门阵列 FPGA - Arria II GX 2530 LABs 364 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| EP2AGX65DF29C6 | 功能描述:FPGA - 现场可编程门阵列 FPGA - Arria II GX 2530 LABs 364 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| EP2AGX65DF29C6N | 功能描述:FPGA - 现场可编程门阵列 FPGA - Arria II GX 2530 LABs 364 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| EP2AGX65DF29C6NES | 制造商:Altera Corporation 功能描述:FPGA Arria |
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