参数资料
| 型号： | EP4CE10F17I7 |
| 厂商： | Altera |
| 文件页数： | 18/42页 |
| 文件大小： | 0K |
| 描述： | IC CYCLONE IV FPGA 10K 256FBGA |
| 产品培训模块： | Three Reasons to Use FPGA's in Industrial Designs Cyclone IV FPGA Family Overview |
| 特色产品： | Cyclone? IV FPGAs |
| 标准包装： | 90 |
| 系列： | CYCLONE® IV E |
| LAB/CLB数： | 645 |
| 逻辑元件/单元数： | 10320 |
| RAM 位总计： | 423936 |
| 输入/输出数： | 179 |
| 电源电压： | 1.15 V ~ 1.25 V |
| 安装类型： | 表面贴装 |
| 工作温度： | -40°C ~ 100°C |
| 封装/外壳： | 256-BGA |
| 供应商设备封装： | 256-FBGA（17x17） |
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Chapter 1: Cyclone IV Device Datasheet
1–25
Switching Characteristics
December 2013
Altera Corporation
tDLOCK
Time required to lock dynamically (after switchover,
reconfiguring any non-post-scale counters/delays or
areset
is deasserted)
——
1
ms
tOUTJITTER_PERIOD_DEDCLK (6)
Dedicated clock output period jitter
FOUT 100 MHz
—
300
ps
FOUT < 100 MHz
—
30
mUI
tOUTJITTER_CCJ_DEDCLK (6)
Dedicated clock output cycle-to-cycle jitter
FOUT 100 MHz
—
300
ps
FOUT < 100 MHz
—
30
mUI
tOUTJITTER_PERIOD_IO (6)
Regular I/O period jitter
FOUT 100 MHz
—
650
ps
FOUT < 100 MHz
—
75
mUI
tOUTJITTER_CCJ_IO (6)
Regular I/O cycle-to-cycle jitter
FOUT 100 MHz
—
650
ps
FOUT < 100 MHz
—
75
mUI
tPLL_PSERR
Accuracy of PLL phase shift
—
±50
ps
tARESET
Minimum pulse width on areset signal.
10
—
ns
tCONFIGPLL
Time required to reconfigure scan chains for PLLs
—
3.5 (7)
—
SCANCLK
cycles
fSCANCLK
scanclk
frequency
—
100
MHz
tCASC_OUTJITTER_PERIOD_DEDCLK
Period jitter for dedicated clock output in cascaded
PLLs (FOUT 100 MHz)
—
425
ps
Period jitter for dedicated clock output in cascaded
PLLs (FOUT 100 MHz)
—
42.5
mUI
Notes to Table 1–25:
(1) This table is applicable for general purpose PLLs and multipurpose PLLs.
(2) You must connect VCCD_PLL to VCCINT through the decoupling capacitor and ferrite bead.
(3) This parameter is limited in the Quartus II software by the I/O maximum frequency. The maximum I/O frequency is different for each I/O
standard.
(4) The VCO frequency reported by the Quartus II software in the PLL Summary section of the compilation report takes into consideration the VCO
post-scale counter K value. Therefore, if the counter K has a value of 2, the frequency reported can be lower than the fVCO specification.
(5) A high input jitter directly affects the PLL output jitter. To have low PLL output clock jitter, you must provide a clean clock source that is less
than 200 ps.
(6) Peak-to-peak jitter with a probability level of 10–12 (14 sigma, 99.99999999974404% confidence level). The output jitter specification applies
to the intrinsic jitter of the PLL when an input jitter of 30 ps is applied.
(7) With 100-MHz scanclk frequency.
(8) The cascaded PLLs specification is applicable only with the following conditions:
■ Upstream PLL—0.59 MHz Upstream PLL bandwidth < 1 MHz
■ Downstream PLL—Downstream PLL bandwidth > 2 MHz
(9) PLL cascading is not supported for transceiver applications.
Table 1–25. PLL Specifications for Cyclone IV Devices (1), (2) (Part 2 of 2)
Symbol
Parameter
Min
Typ
Max
Unit
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相关代理商/技术参数 |
参数描述 |
|---|---|
| EP4CE10F17I7N | 功能描述:FPGA - 现场可编程门阵列 FPGA - Cyclone IV E 645 LABs 179 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| EP4CE10F17I8L | 功能描述:FPGA - 现场可编程门阵列 FPGA - Cyclone IV E 645 LABs 179 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| EP4CE10F17I8LN | 功能描述:FPGA - 现场可编程门阵列 FPGA - Cyclone IV E 645 LABs 179 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| EP4CE10F23C8N | 制造商:ALTERA 制造商全称:Altera Corporation 功能描述:Cyclone IV FPGA Device Faily Overview |
| EP4CE10F23I7N | 制造商:ALTERA 制造商全称:Altera Corporation 功能描述:Cyclone IV Device Datasheet |
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