参数资料
| 型号： | EP4CGX150DF31C8N |
| 厂商： | Altera |
| 文件页数： | 26/42页 |
| 文件大小： | 0K |
| 描述： | IC CYCLONE IV FPGA 150K 896FBGA |
| 产品培训模块： | Three Reasons to Use FPGA's in Industrial Designs Cyclone IV FPGA Family Overview |
| 特色产品： | Cyclone? IV FPGAs |
| 标准包装： | 27 |
| 系列： | CYCLONE® IV GX |
| LAB/CLB数： | 9360 |
| 逻辑元件/单元数： | 149760 |
| RAM 位总计： | 6635520 |
| 输入/输出数： | 475 |
| 电源电压： | 1.16 V ~ 1.24 V |
| 安装类型： | 表面贴装 |
| 工作温度： | 0°C ~ 85°C |
| 封装/外壳： | 896-BBGA |
| 供应商设备封装： | 896-FBGA（31x31） |
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1–32
Chapter 1: Cyclone IV Device Datasheet
Switching Characteristics
December 2013
Altera Corporation
External Memory Interface Specifications
The external memory interfaces for Cyclone IV devices are auto-calibrating and easy
to implement.
tDUTY
—
455545554555455545
55
%
TCCS
—
200
—
200
—
200
—
200
—
200
ps
Output jitter
(peak to peak)
—
500
—
500
—
550
—
600
—
700
ps
tLOCK (2)
—
1—
1
ms
Notes to Table 1–35:
(1) Cyclone IV E—emulated LVDS transmitter is supported at the output pin of all I/O Banks.
Cyclone IV GX—emulated LVDS transmitter is supported at the output pin of I/O Banks 3, 4, 5, 6, 7, 8, and 9.
(2) tLOCK is the time required for the PLL to lock from the end-of-device configuration.
(3) Cyclone IV E 1.0 V core voltage devices only support C8L, C9L, and I8L speed grades. Cyclone IV E 1.2 V core voltage devices only support
C6, C7, C8, I7, and A7 speed grades. Cyclone IV GX devices only support C6, C7, C8, and I7 speed grades.
Table 1–35. Emulated LVDS Transmitter Timing Specifications for Cyclone IV Devices (1), (3) (Part 2 of 2)
Symbol
Modes
C6
C7, I7
C8, A7
C8L, I8L
C9L
Unit
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Table 1–36. LVDS Receiver Timing Specifications for Cyclone IV Devices (1), (3)
Symbol
Modes
C6
C7, I7
C8, A7
C8L, I8L
C9L
Unit
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
fHSCLK (input
clock
frequency)
×10
10
437.5
10
370
10
320
10
320
10
250
MHz
×8
10
437.5
10
370
10
320
10
320
10
250
MHz
×7
10
437.5
10
370
10
320
10
320
10
250
MHz
×4
10
437.5
10
370
10
320
10
320
10
250
MHz
×2
10
437.5
10
370
10
320
10
320
10
250
MHz
×1
10
437.5
10
402.5
10
402.5
10
362
10
265
MHz
HSIODR
×10
100
875
100
740
100
640
100
640
100
500
Mbps
×8
80
875
80
740
80
640
80
640
80
500
Mbps
×7
70
875
70
740
70
640
70
640
70
500
Mbps
×4
40
875
40
740
40
640
40
640
40
500
Mbps
×2
20
875
20
740
20
640
20
640
20
500
Mbps
×1
10
437.5
10
402.5
10
402.5
10
362
10
265
Mbps
SW
—
400
—
400
—
400
—
550
—
640
ps
Input jitter
tolerance
—
500
—
500
—
550
—
600
—
700
ps
tLOCK (2)
—
—1—1—1—1—
1
ms
Notes to Table 1–36:
(1) Cyclone IV E—LVDS receiver is supported at all I/O Banks.
Cyclone IV GX—LVDS receiver is supported at I/O Banks 3, 4, 5, 6, 7, 8, and 9.
(2) tLOCK is the time required for the PLL to lock from the end-of-device configuration.
(3) Cyclone IV E 1.0 V core voltage devices only support C8L, C9L, and I8L speed grades. Cyclone IV E 1.2 V core voltage devices only support
C6, C7, C8, I7, and A7 speed grades. Cyclone IV GX devices only support C6, C7, C8, and I7 speed grades.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| EP4CGX150DF31I7 | 功能描述:FPGA - 现场可编程门阵列 FPGA - Cyclone IV GX 9360 LABs 475 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| EP4CGX150DF31I7N | 功能描述:FPGA - 现场可编程门阵列 FPGA - Cyclone IV GX 9360 LABs 475 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| EP4CGX150F17C8 | 制造商:ALTERA 制造商全称:Altera Corporation 功能描述:Cyclone IV Device Datasheet |
| EP4CGX150F23C8N | 制造商:ALTERA 制造商全称:Altera Corporation 功能描述:Cyclone IV FPGA Device Faily Overview |
| EP4CGX150F23I7N | 制造商:ALTERA 制造商全称:Altera Corporation 功能描述:Cyclone IV Device Datasheet |
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