参数资料
型号: EP4CGX75DF27I7N
厂商: Altera
文件页数: 27/42页
文件大小: 0K
描述: IC CYCLONE IV GX FPGA 75K 672FBG
产品培训模块: Cyclone IV FPGA Family Overview
特色产品: Cyclone? IV FPGAs
标准包装: 40
系列: CYCLONE® IV GX
LAB/CLB数: 4620
逻辑元件/单元数: 73920
RAM 位总计: 4257792
输入/输出数: 310
电源电压: 1.16 V ~ 1.24 V
安装类型: 表面贴装
工作温度: -40°C ~ 100°C
封装/外壳: 672-BGA
供应商设备封装: 672-FBGA(27x27)
Chapter 1: Cyclone IV Device Datasheet
1–33
Switching Characteristics
December 2013
Altera Corporation
f For more information about the supported maximum clock rate, device and pin
planning, IP implementation, and device termination, refer to Section III: System
Performance Specifications of the External Memory Interface Handbook.
Table 1–37 lists the memory output clock jitter specifications for Cyclone IV devices.
Duty Cycle Distortion Specifications
Table 1–38 lists the worst case duty cycle distortion for Cyclone IV devices.
OCT Calibration Timing Specification
Table 1–39 lists the duration of calibration for series OCT with calibration at device
power-up for Cyclone IV devices.
Table 1–37. Memory Output Clock Jitter Specifications for Cyclone IV Devices (1), (2)
Parameter
Symbol
Min
Max
Unit
Clock period jitter
tJIT(per)
–125
125
ps
Cycle-to-cycle period jitter
tJIT(cc)
–200
200
ps
Duty cycle jitter
tJIT(duty)
–150
150
ps
Notes to Table 1–37:
(1) Memory output clock jitter measurements are for 200 consecutive clock cycles, as specified in the JEDEC DDR2
standard.
(2) The clock jitter specification applies to memory output clock pins generated using DDIO circuits clocked by a PLL
output routed on a global clock (GCLK) network.
Table 1–38. Duty Cycle Distortion on Cyclone IV Devices I/O Pins (1), (2), (3)
Symbol
C6
C7, I7
C8, I8L, A7
C9L
Unit
Min
Max
Min
Max
Min
Max
Min
Max
Output Duty Cycle
4555
%
Notes to Table 1–38:
(1) The duty cycle distortion specification applies to clock outputs from the PLLs, global clock tree, and IOE driving the dedicated and general
purpose I/O pins.
(2) Cyclone IV devices meet the specified duty cycle distortion at the maximum output toggle rate for each combination of I/O standard and current
strength.
(3) Cyclone IV E 1.0 V core voltage devices only support C8L, C9L, and I8L speed grades. Cyclone IV E 1.2 V core voltage devices only support
C6, C7, C8, I7, and A7 speed grades. Cyclone IV GX devices only support C6, C7, C8, and I7 speed grades.
Table 1–39. Timing Specification for Series OCT with Calibration at Device Power-Up for
Cyclone IV Devices (1)
Symbol
Description
Maximum
Units
tOCTCAL
Duration of series OCT with
calibration at device power-up
20
s
Note to Table 1–39:
(1) OCT calibration takes place after device configuration and before entering user mode.
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