参数资料
| 型号： | EP4S100G2F40I1 |
| 厂商： | Altera |
| 文件页数： | 21/22页 |
| 文件大小： | 0K |
| 描述： | IC STRATIX IV FPGA 230K 1517FBGA |
| 产品培训模块： | Three Reasons to Use FPGA's in Industrial Designs |
| 标准包装： | 3 |
| 系列： | STRATIX® IV GT |
| LAB/CLB数： | 9120 |
| 逻辑元件/单元数： | 228000 |
| RAM 位总计： | 17544192 |
| 输入/输出数： | 654 |
| 电源电压： | 0.92 V ~ 0.98 V |
| 安装类型： | 表面贴装 |
| 工作温度： | -40°C ~ 100°C |
| 封装/外壳： | 1517-BBGA |
| 供应商设备封装： | 1517-FBGA（40x40） |
1–8
Chapter 1: Overview for the Stratix IV Device Family
Architecture Features
September 2012
Altera Corporation
FPGA Fabric and I/O Features
The following sections describe the Stratix IV FPGA fabric and I/O features.
Device Core Features
■
Up to 531,200 LEs in Stratix IV GX and GT devices and up to 813,050 LEs in
Stratix IV E devices, efficiently packed in unique and innovative adaptive logic
modules (ALMs)
■
Ten ALMs per logic array block (LAB) deliver faster performance, improved logic
utilization, and optimized routing
■
Programmable power technology, including a variety of process, circuit, and
architecture optimizations and innovations
■
Programmable power technology available to select power-driven compilation
options for reduced static power consumption
Embedded Memory
■
TriMatrix embedded memory architecture provides three different memory block
sizes to efficiently address the needs of diversified FPGA designs:
■
640-bit MLAB
■
9-Kb M9K
■
144-Kb M144K
■
Up to 33,294 Kb of embedded memory operating at up to 600 MHz
■
Each memory block is independently configurable to be a single- or dual-port
RAM, FIFO, ROM, or shift register
Digital Signal Processing (DSP) Blocks
■
Flexible DSP blocks configurable as 9 x 9-bit, 12 x 12-bit, 18 x 18-bit, and 36 x 36-bit
full-precision multipliers at up to 600 MHz with rounding and saturation
capabilities
■
Faster operation due to fully pipelined architecture and built-in addition,
subtraction, and accumulation units to combine multiplication results
■
Optimally designed to support advanced features such as adaptive filtering, barrel
shifters, and finite and infinite impulse response (FIR and IIR) filters
Clock Networks
■
Up to 16 global clocks and 88 regional clocks optimally routed to meet the
maximum performance of 800 MHz
■
Up to 112 and 132 periphery clocks in Stratix IV GX and Stratix IV E devices,
respectively
■
Up to 66 (16 GCLK + 22 RCLK + 28 PCLK) clock networks per device quadrant in
Stratix IV GX and Stratix IV GT devices
■
Up to 71 (16 GCLK + 22 RCLK + 33 PCLK) clock networks per device quadrant in
Stratix IV E devices
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相关代理商/技术参数 |
参数描述 |
|---|---|
| EP4S100G2F40I1N | 功能描述:FPGA - 现场可编程门阵列 FPGA - Stratix IV 9120 LABs 654 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| EP4S100G2F40I2 | 功能描述:FPGA - 现场可编程门阵列 FPGA - Stratix IV 9120 LABs 654 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| EP4S100G2F40I2N | 功能描述:FPGA - 现场可编程门阵列 FPGA - Stratix IV 9120 LABs 654 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| EP4S100G3F45I1 | 功能描述:FPGA - 现场可编程门阵列 FPGA - Stratix IV 11648 LABs 781 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| EP4S100G3F45I1N | 功能描述:FPGA - 现场可编程门阵列 FPGA - Stratix IV 11648 LABs 781 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
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