参数资料
| 型号： | EP4SGX290FH29I4 |
| 厂商： | Altera |
| 文件页数： | 53/82页 |
| 文件大小： | 0K |
| 描述： | IC STRATIX IV FPGA 290K 780HBGA |
| 产品培训模块： | Three Reasons to Use FPGA's in Industrial Designs |
| 标准包装： | 3 |
| 系列： | Stratix® IV GX |
| LAB/CLB数： | 11648 |
| 逻辑元件/单元数： | 291200 |
| RAM 位总计： | 17661952 |
| 输入/输出数： | 289 |
| 电源电压： | 0.87 V ~ 0.93 V |
| 安装类型： | 表面贴装 |
| 工作温度： | -40°C ~ 100°C |
| 封装/外壳： | 780-BBGA 裸露焊盘 |
| 供应商设备封装： | 780-HBGA（33x33） |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页当前第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页
Chapter 1: DC and Switching Characteristics for Stratix IV Devices
1–49
Switching Characteristics
March 2014
Altera Corporation
Stratix IV Device Handbook
Volume 4: Device Datasheet and Addendum
tOUTCCJ_DC (6)
Cycle to Cycle Jitter for dedicated clock output
(FOUT ≥ 100 MHz)
—
175
ps (p-p)
Cycle to Cycle Jitter for dedicated clock output
(FOUT < 100 MHz)
—
17.5
mUI (p-p)
tOUTPJ_IO (6),
Period Jitter for clock output on regular I/O
(FOUT ≥ 100 MHz)
—
600
ps (p-p)
Period Jitter for clock output on regular I/O
(FOUT < 100 MHz)
—
60
mUI (p-p)
tOUTCCJ_IO (6),
Cycle to Cycle Jitter for clock output on regular I/O
(FOUT ≥ 100 MHz)
—
600
ps (p-p)
Cycle to Cycle Jitter for clock output on regular I/O
(FOUT < 100 MHz)
—
60
mUI (p-p)
tCASC_OUTPJ_DC
Period Jitter for dedicated clock output in cascaded PLLs
(FOUT ≥100MHz)
—
250
ps (p-p)
Period Jitter for dedicated clock output in cascaded PLLs
(FOUT < 100MHz)
—
25
mUI (p-p)
fDRIFT
Frequency drift after PFDENA is disabled for duration of
100 us
—
±10
%
Notes to Table 1–34:
(1) This specification is limited in the Quartus II software by the I/O maximum frequency. The maximum I/O frequency is different for each I/O
standard.
(2) The VCO frequency reported by the Quartus II software in the PLL summary section of the compilation report takes into consideration the VCO
post-scale counter K value. Therefore, if the counter K has a value of 2, the frequency reported can be lower than the fVCO specification.
(3) This specification is limited by the lower of the two: I/O FMAX or FOUT of the PLL.
(4) A high input jitter directly affects the PLL output jitter. To have low PLL output clock jitter, you must provide a clean clock source that is less
than 120 ps.
(5) FREF is fIN/N when N = 1.
(6) Peak-to-peak jitter with a probability level of 10–12 (14 sigma, 99.99999999974404% confidence level). The output jitter specification applies
to the intrinsic jitter of the PLL, when an input jitter of 30 ps is applied. The external memory interface clock output jitter specifications use a
different measurement method and are available in Table 1–51 on page 1–62.
(7) The cascaded PLL specification is only applicable with the following condition:
A. Upstream PLL: 0.59Mhz
Upstream PLL BW < 1 MHz
B. Downstream PLL: Downstream PLL BW > 2 MHz
(8) High bandwidth PLL settings are not supported in external feedback mode.
(9) External memory interface clock output jitter specifications use a different measurement method, which is available in Table 1–49 on
Table 1–34. PLL Specifications for Stratix IV Devices (Part 2 of 2)
Symbol
Parameter
Min
Typ
Max
Unit
相关PDF资料 |
PDF描述 |
|---|---|
| HSM44DSAH | CONN EDGECARD 88POS R/A .156 SLD |
| HMM44DSAH | CONN EDGECARD 88POS R/A .156 SLD |
| EP4SGX290FH29C3 | IC STRATIX IV FPGA 290K 780HBGA |
| EMC60DRYI-S93 | CONN EDGECARD 120PS DIP .100 SLD |
| 93LC46AT-I/MC | IC EEPROM 1KBIT 2MHZ 8DFN |
相关代理商/技术参数 |
参数描述 |
|---|---|
| EP4SGX290FH29I4N | 功能描述:FPGA - 现场可编程门阵列 FPGA - Stratix IV GX 11648 LABs 289 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| EP4SGX290HF35C2 | 功能描述:FPGA - 现场可编程门阵列 FPGA - Stratix IV GX 11648 LABs 564 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| EP4SGX290HF35C2N | 功能描述:FPGA - 现场可编程门阵列 FPGA - Stratix IV GX 11648 LABs 564 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| EP4SGX290HF35C3 | 功能描述:FPGA - 现场可编程门阵列 FPGA - Stratix IV GX 11648 LABs 564 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| EP4SGX290HF35C3N | 功能描述:FPGA - 现场可编程门阵列 FPGA - Stratix IV GX 11648 LABs 564 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
发布紧急采购，3分钟左右您将得到回复。