参数资料
| 型号： | EP4SGX360FF35C2X |
| 厂商： | Altera |
| 文件页数： | 72/82页 |
| 文件大小： | 0K |
| 描述： | IC STRATIX IV FPGA 360K 1152FBGA |
| 产品培训模块： | Three Reasons to Use FPGA's in Industrial Designs |
| 标准包装： | 3 |
| 系列： | Stratix® IV GX |
| LAB/CLB数： | 14144 |
| 逻辑元件/单元数： | 353600 |
| RAM 位总计： | 23105536 |
| 输入/输出数： | 564 |
| 电源电压： | 0.87 V ~ 0.93 V |
| 安装类型： | 表面贴装 |
| 工作温度： | 0°C ~ 85°C |
| 封装/外壳： | 1152-BBGA |
| 供应商设备封装： | 1152-FBGA（27x27） |
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1–66
Chapter 1: DC and Switching Characteristics for Stratix IV Devices
Glossary
Stratix IV Device Handbook
March 2014
Altera Corporation
Volume 4: Device Datasheet and Addendum
S
SW (sampling
window)
Timing Diagram—the period of time during which the data must be valid in order to capture
it correctly. The setup and hold times determine the ideal strobe position within the sampling
window, as shown:
Single-ended
voltage
referenced I/O
standard
The JEDEC standard for SSTl and HSTL I/O defines both the AC and DC input signal values.
The AC values indicate the voltage levels at which the receiver must meet its timing
specifications. The DC values indicate the voltage levels at which the final logic state of the
receiver is unambiguously defined. After the receiver input has crossed the AC value, the
receiver changes to the new logic state.
The new logic state is then maintained as long as the input stays beyond the AC threshold.
This approach is intended to provide predictable receiver timing in the presence of input
waveform ringing, as shown:
Single-Ended Voltage Referenced I/O Standard
T
tC
High-speed receiver/transmitter input and output clock period.
TCCS (channel-
to-channel-skew)
The timing difference between the fastest and slowest output edges, including tCO variation
and clock skew, across channels driven by the same PLL. The clock is included in the TCCS
measurement (refer to the Timing Diagram figure under SW in this table).
tDUTY
High-speed I/O block: Duty cycle on high-speed transmitter output clock.
Timing Unit Interval (TUI)
The timing budget allowed for skew, propagation delays, and data sampling window.
(TUI = 1/(Receiver Input Clock Frequency Multiplication Factor) = tC/w)
tFALL
Signal high-to-low transition time (80-20%)
tINCCJ
Cycle-to-cycle jitter tolerance on the PLL clock input
tOUTPJ_IO
Period jitter on the general purpose I/O driven by a PLL
tOUTPJ_DC
Period jitter on the dedicated clock output driven by a PLL
tRISE
Signal low-to-high transition time (20-80%)
U
——
Table 1–54. Glossary Table (Part 3 of 4)
Letter
Subject
Definitions
Bit Time
0.5 x TCCS
RSKM
Sampling Window
(SW)
RSKM
0.5 x TCCS
VIH(AC)
VIH(DC)
VREF
VIL(DC)
VIL(AC)
VOH
VOL
VCCIO
VSS
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相关代理商/技术参数 |
参数描述 |
|---|---|
| EP4SGX360FF35C2XN | 功能描述:FPGA - 现场可编程门阵列 FPGA - Stratix IV GX 14144 LABs 564 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| EP4SGX360FF35C3 | 功能描述:FPGA - 现场可编程门阵列 FPGA - Stratix IV GX 14144 LABs 564 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| EP4SGX360FF35C3N | 功能描述:FPGA - 现场可编程门阵列 FPGA - Stratix IV GX 14144 LABs 564 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| EP4SGX360FF35C4 | 功能描述:FPGA - 现场可编程门阵列 FPGA - Stratix IV GX 14144 LABs 564 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| EP4SGX360FF35C4N | 功能描述:FPGA - 现场可编程门阵列 FPGA - Stratix IV GX 14144 LABs 564 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
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