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参数资料
| 型号： | EPC4 |
| 厂商： | Altera Corporation |
| 英文描述： | Configuration Devices for SRAM-Based LUT Devices |
| 中文描述： | 配置SRAM器件基于LUT的器件 |
| 文件页数： | 10/36页 |
| 文件大小： | 283K |
| 代理商： | EPC4 |
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10
Altera Corporation
Configuration Devices for SRAM-based LUT Devices Data Sheet
Table 3
describes EPC2, EPC1, and EPC1441 pin functions during
APEX II, APEX 20K, Mercury, ACEX 1K, and FLEX device configuration.
For information on EPC4, EPC8, and EPC16 devices, refer to
Enhanced
Configuration Devices (EPC4, EPC8, & EPC16) Data Sheet
.
Table 3. EPC2, EPC1, & EPC1441 Pin Functions During APEX II, APEX 20K, Mercury, ACEX 1K, FLEX 10K
& FLEX 6000 Configuration (Part 1 of 3)
Notes (1)
,
(2)
Pin Name
Pin Number
Pin
Type
Description
8-Pin
PDIP
(3)
20-Pin
PLCC
32-Pin
TQFP
(4)
DATA
1
2
31
Output
Serial data output. The
DATA
pin is tri-stated before
configuration when the
nCS
pin is high, and after the
configuration device finishes sending its configuration
data. This operation is independent of the device’s
position in the cascade chain.
DCLK
is a clock output when configuring with a single
configuration device or when the configuration device is
the first device in a configuration device chain.
DCLK
is
a clock input for subsequent configuration devices in a
configuration device chain. Rising edges on
DCLK
increment the internal address counter and present the
next bit of data to the
DATA
pin. The counter is
incremented only if the
OE
input is held high, the
nCS
input is held low, and all configuration data has not
been transferred to the target device. When configuring
with the first EPC2 or EPC1 device in a configuration
device chain or with a single EPC1441 device, the
DCLK
pin drives low after configuration is complete or
when
OE
is low.
Output enable (active high) and reset (active low). A
low logic level resets the address counter. A high logic
level enables
DATA
and permits the address counter to
count. If this pin is low (reset) during configuration, the
internal oscillator becomes inactive and
DCLK
drives
low. See
“Error Detection Circuitry”
on
page 23
.
Chip select input (active low). A low input allows
DCLK
to increment the address counter and enables
DATA
to
drive out. If the EPC1 or EPC2 is reset with
nCS
low, the
device initializes as the first device in a configuration
chain. If the EPC1 or EPC2 device is reset with
nCS
high, the device initializes as the subsequent device in
the chain.
DCLK
2
4
2
I/O
OE
(5)
3
8
7
Open-
Drain
I/O
nCS
(5)
4
9
10
Input
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相关代理商/技术参数 |
参数描述 |
|---|---|
| EPC-4 | 制造商:Curtis Industries 功能描述: |
| EPC40-30B25 | 制造商:Pulse 功能描述:- Bulk |
| EPC-440-0.9 | 制造商:EPIGAP 制造商全称:EPIGAP 功能描述:Photodiode-Chip |
| EPC-440-1.4 | 制造商:EPIGAP 制造商全称:EPIGAP 功能描述:Photodiode-Chip |
| EPC-440-2.5 | 制造商:EPIGAP 制造商全称:EPIGAP 功能描述:Photodiode-Chip |
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