- 您现在的位置：买卖IC网 > PDF目录362744 > EPC4QI100 (Altera Corporation) 2. Enhanced Configuration Devices (EPC4, EPC8 & EPC16) Data Sheet PDF资料下载
参数资料
| 型号： | EPC4QI100 |
| 厂商： | Altera Corporation |
| 英文描述： | 2. Enhanced Configuration Devices (EPC4, EPC8 & EPC16) Data Sheet |
| 中文描述： | 2。增强型配置器件（EPC4，EPC8 |
| 文件页数： | 4/36页 |
| 文件大小： | 421K |
| 代理商： | EPC4QI100 |
第1页第2页第3页当前第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页
2–4
Configuration Handbook, Volume 2
Altera Corporation
August 2005
Functional Description
1
For more information on Stratix Remote System Configuration,
refer to the
Using Remote System Configuration with Stratix &
Stratix GX Devices chapter of the Stratix
Device
Handbook
.
Other user programmable features include:
■
■
■
■
Real-time decompression of configuration data
Programmable configuration clock (
DCLK
)
Flash ISP
Programmable power-on-reset delay (
PORSEL
)
FPGA Configuration
FPGA configuration is managed by the configuration controller chip.
This process includes reading configuration data from the flash memory,
decompressing it if necessary, transmitting configuration data via the
appropriate
DATA[]
pins, and handling errors conditions.
After POR, the controller determines the user-defined configuration
options by reading its option bits from the flash memory. These options
include the configuration scheme, configuration clock speed,
decompression, and configuration page settings. The option bits are
stored at flash address location 0x8000 (word address) and occupy
512-bits or 32-words of memory. These options bits are read using the
internal flash interface and the default 10 MHz internal oscillator.
After obtaining the configuration settings, it checks if the FPGA is ready
to accept configuration data by monitoring the
nSTATUS
and
CONF_DONE
lines. When the FPGA is ready (
nSTATUS
is high and
CONF_DONE
is low), the controller begins data transfer using the
DCLK
and
DATA[]
output pins. The controller selects the configuration page to
be transmitted to the FPGA(s) by sampling its
PGM[2..0]
pins after POR
or reset.
The function of the configuration unit is to transmit decompressed data
to the FPGA, depending on the configuration scheme. The enhanced
configuration device supports four concurrent configuration modes, with
n = 1, 2, 4, or 8 (where n is the number of bits that are sent per
DCLK
cycle
on the
DATA[n]
lines). The value n=1 corresponds to the traditional PS
configuration scheme. The values n=2, 4, and 8 correspond to concurrent
configuration of 2, 4, or 8 different PS configuration chains, respectively.
Additionally, the FPGA can be configured in FPP mode, where eight bits
of
DATA
are clocked into the FPGA per
DCLK
cycle. Depending on the
configuration bus width (n), the circuit shifts uncompressed
configuration data to the valid
DATA[n]
pins. Unused
DATA[]
pins drive
low.
相关PDF资料 |
PDF描述 |
|---|---|
| EPC16UC88 | 2. Enhanced Configuration Devices (EPC4, EPC8 & EPC16) Data Sheet |
| EPCS1 | Serial Configuration Devices |
| EPCS16 | Serial Configuration Devices |
| EPCS16SI16N | Serial Configuration Devices |
| EPCS1SI8N | Serial Configuration Devices |
相关代理商/技术参数 |
参数描述 |
|---|---|
| EPC4QI100N | 功能描述:FPGA-配置存储器 IC - Ser. Config Mem Flash 4Mb 66 MHz RoHS:否 制造商:Altera Corporation 存储类型:Flash 存储容量:1.6 Mbit 工作频率:10 MHz 电源电压-最大:5.25 V 电源电压-最小:3 V 电源电流:50 uA 最大工作温度:+ 85 C 最小工作温度:- 40 C 安装风格:SMD/SMT 封装 / 箱体:PLCC-20 |
| EPC4XXX | 制造商:ALTERA 制造商全称:Altera Corporation 功能描述:2. Enhanced Configuration Devices (EPC4, EPC8 & EPC16) Data Sheet |
| EPC50C605 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| EPC-525-0.5 | 制造商:EPIGAP 制造商全称:EPIGAP 功能描述:Photodiode-Chip |
| EPC-525-0.5-2 | 制造商:EPIGAP 制造商全称:EPIGAP 功能描述:Photodiode-Chip |
发布紧急采购，3分钟左右您将得到回复。