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| 型号： | EPC8QI100N |
| 厂商： | Altera |
| 文件页数： | 12/36页 |
| 文件大小： | 0K |
| 描述： | IC CONFIG DEVICE 8MBIT 100-PQFP |
| 产品培训模块： | Three Reasons to Use FPGA's in Industrial Designs |
| 标准包装： | 66 |
| 系列： | EPC |
| 可编程类型： | 系统内可编程 |
| 存储容量： | 8Mb |
| 电源电压： | 3 V ~ 3.6 V |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 100-BQFP |
| 供应商设备封装： | 100-PQFP（14x20） |
| 包装： | 托盘 |
| 其它名称： | 544-1682 |
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Page 2
Functional Description
Enhanced Configuration (EPC) Devices Datasheet
January 2012
Altera Corporation
■
Pin selectable 2-ms or 100-ms power-on reset (POR) time
■
Configuration clock supports programmable input source and frequency synthesis
■
Multiple configuration clock sources supported (internal oscillator and
external clock input pin)
■
External clock source with frequencies up to 100 MHz
■
Internal oscillator defaults to 10 MHz and you can program the internal
oscillator for higher frequencies of 33, 50, and 66 MHz
■
Clock synthesis supported using user programmable divide counter
■
Available in the 100-pin plastic quad flat pack (PQFP) and the 88-pin Ultra
FineLine BGA (UFBGA) packages
■
Vertical migration between all devices supported in the 100-pin PQFP package
■
Supply voltage of 3.3 V (core and I/O)
■
Hardware compliant with IEEE Std. 1532 in-system programmability (ISP)
specification
■
Supports ISP using Jam Standard Test and Programming Language (STAPL)
■
Supports JTAG boundary scan
■
The nINIT_CONF pin allows private JTAG instruction to start FPGA configuration
■
Internal pull-up resistor on the nINIT_CONF pin always enabled
■
User programmable weak internal pull-up resistors on nCS and OE pins
■
Internal weak pull-up resistors on external flash interface address and control
lines, bus hold on data lines
■
Standby mode with reduced power consumption
f For more information about FPGA configuration schemes and advanced features,
refer to the configuration chapter in the appropriate device handbook.
Functional Description
The Altera EPC device is a single device with high speed and advanced configuration
solution for high-density FPGAs. The core of an EPC device is divided into two major
blocks—a configuration controller and a flash memory. The flash memory is used to
store configuration data for systems made up of one or more than one Altera FPGAs.
Unused portions of the flash memory can be used to store processor code or data that
can be accessed using the external flash interface after the FPGA configuration is
complete.
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