参数资料
型号: EPF10K30EQC208-2X
厂商: Altera
文件页数: 4/100页
文件大小: 0K
描述: IC FLEX 10KE FPGA 30K 208-PQFP
产品培训模块: Three Reasons to Use FPGA's in Industrial Designs
标准包装: 72
系列: FLEX-10KE®
LAB/CLB数: 216
逻辑元件/单元数: 1728
RAM 位总计: 24576
输入/输出数: 147
门数: 119000
电源电压: 2.375 V ~ 2.625 V
安装类型: 表面贴装
工作温度: 0°C ~ 85°C
封装/外壳: 208-BFQFP
供应商设备封装: 208-PQFP(28x28)
Altera Corporation
11
FLEX 10KE Embedded Programmable Logic Devices Data Sheet
The EAB can also be used for bidirectional, dual-port memory
applications where two ports read or write simultaneously. To implement
this type of dual-port memory, two EABs are used to support two
simultaneous read or writes.
Alternatively, one clock and clock enable can be used to control the input
registers of the EAB, while a different clock and clock enable control the
output registers (see Figure 2).
Figure 2. FLEX 10KE Device in Dual-Port RAM Mode
Notes:
(1)
All registers can be asynchronously cleared by EAB local interconnect signals, global signals, or the chip-wide reset.
(2)
EPF10K30E and EPF10K50E devices have 88 EAB local interconnect channels; EPF10K100E, EPF10K130E, and
EPF10K200E devices have 104 EAB local interconnect channels.
Column Interconnect
EAB Local
Interconnect (2)
Dedicated Clocks
24
D
ENA
Q
D
ENA
Q
D
ENA
Q
D
ENA
Q
D
ENA
Q
data[ ]
rdaddress[ ]
wraddress[ ]
RAM/ROM
256
× 16
512
× 8
1,024
× 4
2,048
× 2
Data In
Read Address
Write Address
Read Enable
Write Enable
Data Out
4, 8, 16, 32
outclocken
inclocken
inclock
outclock
D
ENA
Q
Write
Pulse
Generator
rden
wren
Multiplexers allow read
address and read
enable registers to be
clocked by inclock or
outclock signals.
Row Interconnect
4, 8
Dedicated Inputs &
Global Signals
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