收藏本站
参数资料
型号： EPF10K50SFC256-1X
英文描述： Field Programmable Gate Array (FPGA)
中文描述： 现场可编程门阵列（FPGA）
文件页数： 60/120页
文件大小： 1901K
代理商： EPF10K50SFC256-1X
44
Altera Corporation
FLEX 10KE Embedded Programmable Logic Family Data Sheet
IEEE Std.
1149.1 (JTAG)
Boundary-Scan
Support
All FLEX 10KE devices provide JTAG BST circuitry that complies with the
IEEE Std. 1149.1-1990 specification. FLEX 10KE devices can also be
configured using the JTAG pins through the BitBlaster or ByteBlasterMV
download cable, or via hardware that uses the JamTM programming and
test language. JTAG boundary-scan testing can be performed before or
after configuration, but not during configuration. FLEX 10KE devices
support the JTAG instructions shown in Table 15.
The instruction register length of FLEX 10KE devices is 10 bits. The
USERCODE register length in FLEX 10KE devices is 32 bits; 7 bits are
determined by the user, and 25 bits are pre-determined. Tables 16 and 17
show the boundary-scan register length and device IDCODE information
for FLEX 10KE devices.
Table 15. FLEX 10KE JTAG Instructions
JTAG Instruction
Description
SAMPLE/PRELOAD
Allows a snapshot of signals at the device pins to be captured and examined during
normal device operation, and permits an initial data pattern to be output at the device
pins.
EXTEST
Allows the external circuitry and board-level interconnections to be tested by forcing a
test pattern at the output pins and capturing test results at the input pins.
BYPASS
Places the 1-bit bypass register between the TDI and TDO pins, which allows the BST
data to pass synchronously through a selected device to adjacent devices during normal
device operation.
USERCODE
Selects the user electronic signature (USERCODE) register and places it between the
TDI
and TDO pins, allowing the USERCODE to be serially shifted out of TDO.
IDCODE
Selects the IDCODE register and places it between TDI and TDO, allowing the IDCODE
to be serially shifted out of TDO.
ICR Instructions
These instructions are used when configuring a FLEX 10KE device via JTAG ports with
a BitBlaster or ByteBlasterMV download cable, or using a Jam File (.jam) or
Jam Byte-Code File (.jbc) via an embedded processor.
Table 16. FLEX 10KE Boundary-Scan Register Length
Device
Boundary-Scan Register Length
EPF10K30E
690
EPF10K50E
EPF10K50S
798
EPF10K100B
873
EPF10K100E
1,050
EPF10K130E
1,308
EPF10K200E
EPF10K200S
1,446
相关PDF资料
PDF描述
EPF10K50SFC256-2 Field Programmable Gate Array (FPGA)
EPF10K50SFC256-2X Field Programmable Gate Array (FPGA)
EPF10K50SFC256-3 Field Programmable Gate Array (FPGA)
EPF10K50SFC484-1 Field Programmable Gate Array (FPGA)
EPF10K50SFC484-1X Field Programmable Gate Array (FPGA)
相关代理商/技术参数
参数描述
EPF10K50SFC256-2 功能描述:FPGA - 现场可编程门阵列 FPGA - Flex 10K 360 LABs 191 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256
EPF10K50SFC256-2X 功能描述:FPGA - 现场可编程门阵列 FPGA - Flex 10K 360 LABs 191 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256
EPF10K50SFC256-3 功能描述:FPGA - 现场可编程门阵列 FPGA - Flex 10K 360 LABs 191 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256
EPF10K50SFC484-1 功能描述:FPGA - 现场可编程门阵列 FPGA - Flex 10K 360 LABs 254 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256
EPF10K50SFC484-1N 功能描述:FPGA - 现场可编程门阵列 FPGA - Flex 10K 360 LABs 254 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256
发布紧急采购，3分钟左右您将得到回复。

采购需求

(若只采购一条型号，填写一行即可)

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

*型号 *数量 厂商 批号 封装
添加更多采购

我的联系方式

*
*
*