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| 型号： | EPF6016 |
| 厂商： | Altera Corporation |
| 英文描述： | Programmable Logic Device Family(FLEX6000可编程逻辑系列器件) |
| 中文描述： | 可编程逻辑器件系列（FLEX6000可编程逻辑系列器件） |
| 文件页数： | 16/59页 |
| 文件大小： | 1051K |
| 代理商： | EPF6016 |
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Altera Corporation
FLEX 6000 Programmable Logic Device Family Data Sheet
Normal Mode
The normal mode is suitable for general logic applications, combinatorial
functions, or wide decoding functions that can take advantage of a
cascade chain. In normal mode, four data inputs from the LAB local
interconnect and the carry-in are inputs to a 4-input LUT. The
MAX+PLUS II or Quartus Compiler automatically selects the carry-in or
the
DATA3
signal as one of the inputs to the LUT. The LUT output can be
combined with the cascade-in signal to form a cascade chain through the
cascade-out signal.
Arithmetic Mode
The arithmetic mode is ideal for implementing adders, accumulators, and
comparators. An LE in arithmetic mode uses two 3-input LUTs. One LUT
computes a 3-input function; the other generates a carry output. As shown
in
Figure 7
, the first LUT uses the carry-in signal and two data inputs from
the LAB local interconnect to generate a combinatorial or registered
output. For example, when implementing an adder, this output is the sum
of three signals:
DATA1
,
DATA2
, and carry-in. The second LUT uses the
same three signals to generate a carry-out signal, thereby creating a carry
chain. The arithmetic mode also supports simultaneous use of the cascade
chain.
The MAX+PLUS II or Quartus software implements logic functions to use
the arithmetic mode automatically where appropriate; the designer does
not have to decide how the carry chain will be used.
Counter Mode
The counter mode offers counter enable, synchronous up/down control,
synchronous clear, and synchronous load options. The counter enable and
synchronous up/down control signals are generated from the data inputs
of the LAB local interconnect. The synchronous clear and synchronous
load options are LAB-wide signals that affect all registers in the LAB.
Consequently, if any of the LEs in a LAB use counter mode, other LEs in
that LAB must be used as part of the same counter or be used for a
combinatorial function. In addition, the MAX+PLUS II or Quartus
Compiler automatically places registers that are not in the counter into
other LABs.
The counter mode uses two 3-input LUTs: one generates the counter data
and the other generates the fast carry bit. A 2-to-1 multiplexer provides
synchronous loading, and another
AND
gate provides synchronous
clearing. If the cascade function is used by an LE in counter mode, the
synchronous clear or load will override any signal carried on the cascade
chain. The synchronous clear overrides the synchronous load.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| EPF6016A | 制造商:ALTERA 制造商全称:Altera Corporation 功能描述:Programmable Logic Device Family |
| EPF6016AFC100-1 | 功能描述:FPGA - 现场可编程门阵列 FPGA - Flex 6000 132 LABs 81 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| EPF6016AFC100-2 | 功能描述:FPGA - 现场可编程门阵列 FPGA - Flex 6000 132 LABs 81 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| EPF6016AFC100-3 | 功能描述:FPGA - 现场可编程门阵列 FPGA - Flex 6000 132 LABs 81 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| EPF6016AFC100-3N | 制造商:Altera Corporation 功能描述: |
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