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| 型号： | EPF6016 |
| 厂商： | Altera Corporation |
| 英文描述： | Programmable Logic Device Family(FLEX6000可编程逻辑系列器件) |
| 中文描述： | 可编程逻辑器件系列（FLEX6000可编程逻辑系列器件） |
| 文件页数： | 17/59页 |
| 文件大小： | 1051K |
| 代理商： | EPF6016 |
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Altera Corporation
17
FLEX 6000 Programmable Logic Device Family Data Sheet
Either the counter enable or up/down control may be used for a given
counter. Moreover, the synchronous load can be used as a count enable by
routing the register output into the data input automatically when
requested by the designer.
The second LE of each LAB has a special function for counter mode; the
carry-in of the LE can be driven by a fast feedback path from the register.
This function gives a faster counter speed for counter carry chains starting
in the second LE of an LAB.
The MAX+PLUS II or Quartus software implements functions to use the
counter mode automatically where appropriate. The designer does not
have to decide how the carry chain will be used.
Internal Tri-State Emulation
Internal tri-state emulation provides internal tri-states without the
limitations of a physical tri-state bus. In a physical tri-state bus, the
tri-state buffers’ output enable (OE) signals select which signal drives the
bus. However, if multiple OE signals are active, contending signals can be
driven onto the bus. Conversely, if no OE signals are active, the bus will
float. Internal tri-state emulation resolves contending tri-state buffers to a
low value and floating buses to a high value, thereby eliminating these
problems. The MAX+PLUS II or Quartus software automatically
implements tri-state bus functionality with a multiplexer.
Clear & Preset Logic Control
Logic for the programmable register’s clear and preset functions is
controlled by the LAB-wide signals
LABCTRL1
and
LABCTRL2
. The LE
register has an asynchronous clear that can implement an asynchronous
preset. Either
LABCTRL1
or
LABCTRL2
can control the asynchronous clear
or preset. Because the clear and preset functions are active-low, the
MAX+PLUS II or Quartus Compiler automatically assigns a logic high to
an unused clear or preset signal. The clear and preset logic is implemented
in either the asynchronous clear or asynchronous preset mode, which is
chosen during design entry (see
Figure 8
).
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相关代理商/技术参数 |
参数描述 |
|---|---|
| EPF6016A | 制造商:ALTERA 制造商全称:Altera Corporation 功能描述:Programmable Logic Device Family |
| EPF6016AFC100-1 | 功能描述:FPGA - 现场可编程门阵列 FPGA - Flex 6000 132 LABs 81 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| EPF6016AFC100-2 | 功能描述:FPGA - 现场可编程门阵列 FPGA - Flex 6000 132 LABs 81 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| EPF6016AFC100-3 | 功能描述:FPGA - 现场可编程门阵列 FPGA - Flex 6000 132 LABs 81 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| EPF6016AFC100-3N | 制造商:Altera Corporation 功能描述: |
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