参数资料
型号: EPF6016AQI208-2
厂商: Altera
文件页数: 30/52页
文件大小: 0K
描述: IC FLEX 6000 FPGA 16K 208-PQFP
标准包装: 24
系列: FLEX 6000
LAB/CLB数: 132
逻辑元件/单元数: 1320
输入/输出数: 171
门数: 16000
电源电压: 3 V ~ 3.6 V
安装类型: 表面贴装
工作温度: -40°C ~ 100°C
封装/外壳: 208-BFQFP
供应商设备封装: 208-PQFP(28x28)
36
Altera Corporation
FLEX 6000 Programmable Logic Device Family Data Sheet
Timing Model
The continuous, high-performance FastTrack Interconnect routing
resources ensure predictable performance and accurate simulation and
timing analysis. This predictable performance contrasts with that of
FPGAs, which use a segmented connection scheme and therefore have
unpredictable performance.
Device performance can be estimated by following the signal path from a
source, through the interconnect, to the destination. For example, the
registered performance between two LEs on the same row can be
calculated by adding the following parameters:
LE register clock-to-output delay (tCO + tREG_TO_OUT)
Routing delay (tROW + tLOCAL)
LE LUT delay (tDATA_TO_REG)
LE register setup time (tSU)
The routing delay depends on the placement of the source and destination
LEs. A more complex registered path may involve multiple combinatorial
LEs between the source and destination LEs.
Timing simulation and delay prediction are available with the Simulator
and Timing Analyzer, or with industry-standard EDA tools. The
Simulator offers both pre-synthesis functional simulation to evaluate logic
design accuracy and post-synthesis timing simulation with 0.1-ns
resolution. The Timing Analyzer provides point-to-point timing delay
information, setup and hold time analysis, and device-wide performance
analysis.
Figure 19 shows the overall timing model, which maps the possible
routing paths to and from the various elements of the FLEX 6000 device.
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