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参数资料
| 型号： | EPM3032ALC44-7 |
| 英文描述： | Electrically-Erasable Complex PLD |
| 中文描述： | 电可擦除复杂可编程逻辑器件 |
| 文件页数： | 12/53页 |
| 文件大小： | 839K |
| 代理商： | EPM3032ALC44-7 |
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Altera Corporation
MAX 3000A Programmable Logic Device Family Data Sheet
...and More
Features
s
Programmable macrocell flipflops with individual clear, preset,
clock, and clock enable controls
s
Programmable power-saving mode for a power reduction of over
50% in each macrocell
s
Configurable expander product-term distribution, allowing up to
32 product terms per macrocell
s
Programmable security bit for protection of proprietary designs
s
Enhanced architectural features, including:
–
6 pin- or logic-driven output enable signals
–
Two global clock signals with optional inversion
–
Enhanced interconnect resources for improved routability
–
Programmable output slew-rate control
s
Software design support and automatic place-and-route provided by
the Altera MAX+PLUS II development system for Windows-based
PCs and Sun SPARCstations, HP 9000 Series 700/800, and IBM RISC
System/6000 workstations
s
Additional design entry and simulation support provided by EDIF
2 0 0 and 3 0 0 netlist files, library of parameterized modules (LPM),
Verilog HDL, VHDL, and other interfaces to popular EDA tools from
third-party manufacturers such as Cadence, Exemplar Logic, Mentor
Graphics, OrCAD, Synopsys, Synplicity, and VeriBest
s
Programming support with the Altera master programming unit
(MPU), MasterBlasterTM communications cable, ByteBlasterMVTM
parallel port download cable, BitBlasterTM serial download cable as
well as programming hardware from third-party manufacturers and
any in-circuit tester that supports JamTM Standard Test and
Programming Language (STAPL) Files (.jam), Jam STAPL Byte-Code
Files (.jbc), or Serial Vector Format Files (.svf)
General
Description
MAX 3000A devices are low-cost, high-performance devices based on the
Altera MAX architecture. Fabricated with advanced CMOS technology,
the EEPROM-based MAX 3000A devices operate with a 3.3-V supply
voltage and provide 600 to 5,000 usable gates, ISP, pin-to-pin delays as
fast as 4.5 ns, and counter speeds of up to 227.3 MHz. MAX 3000A devices
in the -4, -5, -6, -7, and -10 speed grades are compatible with the timing
requirements of the PCI Special Interest Group (PCI SIG) PCI Local Bus
Specification, Revision 2.2
. See Table 2.
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| EPM3032ATC44-10 | |
| EPM3064ATC44-4 | |
| EPM3064ATC44-7 | Electrically-Erasable Complex PLD |
| EPM3128ATC100-10 | |
| EPM3128ATC100-5 | Electrically-Erasable Complex PLD |
相关代理商/技术参数 |
参数描述 |
|---|---|
| EPM3032ALC44-7N | 功能描述:CPLD - 复杂可编程逻辑器件 CPLD - MAX 3000A 32 Macro 34 IOs RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100 |
| EPM3032ALI44-10 | 功能描述:IC MAX 3000A CPLD 32 44-PLCC RoHS:否 类别:集成电路 (IC) >> 嵌入式 - CPLD（复杂可编程逻辑器件） 系列:MAX® 3000A 标准包装:24 系列:CoolRunner II 可编程类型:系统内可编程 最大延迟时间 tpd(1):7.1ns 电压电源 - 内部:1.7 V ~ 1.9 V 逻辑元件/逻辑块数目:24 宏单元数:384 门数:9000 输入/输出数:173 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:208-BFQFP 供应商设备封装:208-PQFP（28x28） 包装:托盘 |
| EPM3032ALI44-10N | 功能描述:CPLD - 复杂可编程逻辑器件 CPLD - MAX 3000A 32 Macro 34 IOs RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100 |
| EPM3032ATC100-5N | 制造商:ALTERA 制造商全称:Altera Corporation 功能描述:Higha??performance, lowa??cost CMOS EEPROMa??based programmable |
| EPM3032ATC4410 | 制造商:ALTERA 功能描述:New 制造商:Altera Corporation 功能描述: |
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