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参数资料
型号： EPM3128ATC144-7
文件页数： 5/53页
文件大小： 839K
代理商： EPM3128ATC144-7
Altera Corporation
13
MAX 3000A Programmable Logic Device Family Data Sheet
The MAX+PLUS II software can use text- or waveform-format test vectors
created with the MAX+PLUS II Text Editor or Waveform Editor to test the
programmed device. For added design verification, designers can
perform functional testing to compare the functional device behavior with
the results of simulation.
Data I/O, BP Microsystems, and other programming hardware
manufacturers also provide programming support for Altera devices.
f For more information, see Programming Hardware Manufacturers.
IEEE Std.
1149.1 (JTAG)
Boundary-Scan
Support
MAX 3000A devices include the JTAG BST circuitry defined by IEEE Std.
1149.1-1990. Table 4 describes the JTAG instructions supported by
MAX 3000A devices. The pin-out tables starting on page 39 of this data
sheet show the location of the JTAG control pins for each device. If the
JTAG interface is not required, the JTAG pins are available as user I/O
pins.
The instruction register length of MAX 3000A devices is 10 bits. The
IDCODE and USERCODE register length is 32 bits. Tables 5 and 6 show
the boundary-scan register length and device IDCODE information for
MAX 3000A devices.
Table 4. MAX 3000A JTAG Instructions
JTAG Instruction
Description
SAMPLE/PRELOAD
Allows a snapshot of signals at the device pins to be captured and examined during
normal device operation, and permits an initial data pattern output at the device pins
EXTEST
Allows the external circuitry and board-level interconnections to be tested by forcing a
test pattern at the output pins and capturing test results at the input pins
BYPASS
Places the 1-bit bypass register between the TDI and TDO pins, which allows the BST
data to pass synchronously through a selected device to adjacent devices during normal
device operation
IDCODE
Selects the IDCODE register and places it between the TDI and TDO pins, allowing the
IDCODE to be serially shifted out of TDO
USERCODE
Selects the 32-bit USERCODE register and places it between the TDI and TDO pins,
allowing the USERCODE value to be shifted out of TDO
ISP Instructions
These instructions are used when programming MAX 3000A devices via the JTAG ports
with the MasterBlaster, ByteBlasterMV, or BitBlaster cable, or when using a Jam STAPL
file, JBC file, or SVF file via an embedded processor or test equipment
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参数描述
EPM3128ATC144-7N 功能描述:CPLD - 复杂可编程逻辑器件 CPLD - MAX 3000A 128 Macro 96 IOs RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100
EPM3128ATI100-10 功能描述:CPLD - 复杂可编程逻辑器件 CPLD - MAX 3000A 128 Macro 80 IOs RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100
EPM3128ATI10010N 制造商:Altera Corporation 功能描述:CPLD MAX 3000A Family 2.5K Gates 128 Macro Cells 98MHz CMOS Technology 3.3V 100-Pin TQFP 制造商:Altera Corporation 功能描述:CPLD MAX 3000A Family 2.5K Gates 128 Macro Cells 98MHz 3.3V 100-Pin TQFP 制造商:Altera 功能描述:CPLD MAX 3000A Family 2.5K Gates 128 Macro Cells 98MHz CMOS Technology 3.3V 100-Pin TQFP 制造商:Altera 功能描述:CPLD MAX 3000A Family 2.5K Gates 128 Macro Cells 98MHz 3.3V 100-Pin TQFP
EPM3128ATI100-10N 功能描述:CPLD - 复杂可编程逻辑器件 CPLD - MAX 3000A 128 Macro 80 IOs RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100
EPM3128ATI144-10 功能描述:CPLD - 复杂可编程逻辑器件 CPLD - MAX 3000A 128 Macro 96 IOs RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100
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