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| 型号： | EPM3128ATI100-10N |
| 厂商： | Altera |
| 文件页数： | 14/46页 |
| 文件大小： | 0K |
| 描述： | IC MAX 3000A CPLD 128 100-TQFP |
| 产品变化通告： | Bond Wire Change 4/Sept/2008 |
| 标准包装： | 270 |
| 系列： | MAX® 3000A |
| 可编程类型： | 系统内可编程 |
| 最大延迟时间 tpd(1)： | 10.0ns |
| 电压电源 - 内部： | 3 V ~ 3.6 V |
| 逻辑元件/逻辑块数目： | 8 |
| 宏单元数： | 128 |
| 门数： | 2500 |
| 输入/输出数： | 80 |
| 工作温度： | -40°C ~ 100°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 100-TQFP |
| 供应商设备封装： | 100-TQFP（14x14） |
| 包装： | 托盘 |
| 产品目录页面： | 603 (CN2011-ZH PDF) |
| 其它名称： | 544-1987 EPM3128ATI100-10N-ND |
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Altera Corporation
21
MAX 3000A Programmable Logic Device Family Data Sheet
Open–Drain Output Option
MAX 3000A devices provide an optional open–drain (equivalent to
open-collector) output for each I/O pin. This open–drain output enables
the device to provide system–level control signals (e.g., interrupt and
write enable signals) that can be asserted by any of several devices. It can
also provide an additional wired–OR plane.
Open-drain output pins on MAX 3000A devices (with a pull-up resistor to
the 5.0-V supply) can drive 5.0-V CMOS input pins that require a high VIH.
When the open-drain pin is active, it will drive low. When the pin is
inactive, the resistor will pull up the trace to 5.0 V, thereby meeting CMOS
requirements. The open-drain pin will only drive low or tri-state; it will
never drive high. The rise time is dependent on the value of the pull-up
resistor and load impedance. The IOL current specification should be
considered when selecting a pull-up resistor
Slew–Rate Control
The output buffer for each MAX 3000A I/O pin has an adjustable output
slew rate that can be configured for low–noise or high–speed
performance. A faster slew rate provides high–speed transitions for
high-performance systems. However, these fast transitions may introduce
noise transients into the system. A slow slew rate reduces system noise,
but adds a nominal delay of 4 to 5 ns. When the configuration cell is
turned off, the slew rate is set for low–noise performance. Each I/O pin
has an individual EEPROM bit that controls the slew rate, allowing
designers to specify the slew rate on a pin–by–pin basis. The slew rate
control affects both the rising and falling edges of the output signal.
Design Security
All MAX 3000A devices contain a programmable security bit that controls
access to the data programmed into the device. When this bit is
programmed, a design implemented in the device cannot be copied or
retrieved. This feature provides a high level of design security because
programmed data within EEPROM cells is invisible. The security bit that
controls this function, as well as all other programmed data, is reset only
when the device is reprogrammed.
Generic Testing
MAX 3000A devices are fully tested. Complete testing of each
programmable EEPROM bit and all internal logic elements ensures 100%
programming yield. AC test measurements are taken under conditions
equivalent to those shown in Figure 8. Test patterns can be used and then
erased during early stages of the production flow.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| EPM3128ATI144-10 | 功能描述:CPLD - 复杂可编程逻辑器件 CPLD - MAX 3000A 128 Macro 96 IOs RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100 |
| EPM3128ATI144-10N | 功能描述:CPLD - 复杂可编程逻辑器件 CPLD - MAX 3000A 128 Macro 96 IOs RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100 |
| EPM3256A | 制造商:ALTERA 制造商全称:Altera Corporation 功能描述:Programmable Logic Device Family |
| EPM3256AFC256-10 | 功能描述:CPLD - 复杂可编程逻辑器件 CPLD - MAX 3000A 256 Macro 161 IOs RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100 |
| EPM3256AFC256-7 | 功能描述:CPLD - 复杂可编程逻辑器件 CPLD - MAX 3000A 256 Macro 161 IOs RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100 |
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