参数资料
型号: EPM7064AELC44-4
厂商: Altera
文件页数: 5/64页
文件大小: 0K
描述: IC MAX 7000 CPLD 64 44-PLCC
标准包装: 390
系列: MAX® 7000A
可编程类型: 系统内可编程
最大延迟时间 tpd(1): 4.5ns
电压电源 - 内部: 3 V ~ 3.6 V
逻辑元件/逻辑块数目: 4
宏单元数: 64
门数: 1250
输入/输出数: 36
工作温度: 0°C ~ 70°C
安装类型: 表面贴装
封装/外壳: 44-LCC(J 形引线)
供应商设备封装: 44-PLCC(16.58x16.58)
包装: 管件
Altera Corporation
13
MAX 7000A Programmable Logic Device Data Sheet
Figure 5. MAX 7000A PIA Routing
While the routing delays of channel-based routing schemes in masked or
FPGAs are cumulative, variable, and path-dependent, the MAX 7000A
PIA has a predictable delay. The PIA makes a design’s timing
performance easy to predict.
I/O Control Blocks
The I/O control block allows each I/O pin to be individually configured
for input, output, or bidirectional operation. All I/O pins have a tri-state
buffer that is individually controlled by one of the global output enable
signals or directly connected to ground or VCC. Figure 6 shows the I/O
control block for MAX 7000A devices. The I/O control block has 6 or
10 global output enable signals that are driven by the true or complement
of two output enable signals, a subset of the I/O pins, or a subset of the
I/O macrocells.
To LAB
PIA Signals
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相关代理商/技术参数
参数描述
EPM7064AELC44-5 制造商:未知厂家 制造商全称:未知厂家 功能描述:Electrically-Erasable Complex PLD
EPM7064AELC44-7 功能描述:CPLD - 复杂可编程逻辑器件 CPLD - MAX 7000 64 Macro 36 IOs RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100
EPM7064AELC84-10 制造商:未知厂家 制造商全称:未知厂家 功能描述:Electrically-Erasable Complex PLD
EPM7064AELC84-4 制造商:未知厂家 制造商全称:未知厂家 功能描述:Electrically-Erasable Complex PLD
EPM7064AELC84-5 制造商:未知厂家 制造商全称:未知厂家 功能描述:Electrically-Erasable Complex PLD