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| 型号： | EPM7064AELC44-4 |
| 厂商： | Altera |
| 文件页数： | 8/64页 |
| 文件大小： | 0K |
| 描述： | IC MAX 7000 CPLD 64 44-PLCC |
| 标准包装： | 390 |
| 系列： | MAX® 7000A |
| 可编程类型： | 系统内可编程 |
| 最大延迟时间 tpd(1)： | 4.5ns |
| 电压电源 - 内部： | 3 V ~ 3.6 V |
| 逻辑元件/逻辑块数目： | 4 |
| 宏单元数： | 64 |
| 门数： | 1250 |
| 输入/输出数： | 36 |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 44-LCC（J 形引线） |
| 供应商设备封装： | 44-PLCC（16.58x16.58） |
| 包装： | 管件 |
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16
Altera Corporation
MAX 7000A Programmable Logic Device Data Sheet
In-System
Programma-
bility
MAX 7000A devices can be programmed in-system via an industry-
standard 4-pin IEEE Std. 1149.1 (JTAG) interface. ISP offers quick, efficient
iterations during design development and debugging cycles. The
MAX 7000A architecture internally generates the high programming
voltages required to program EEPROM cells, allowing in-system
programming with only a single 3.3-V power supply. During in-system
programming, the I/O pins are tri-stated and weakly pulled-up to
eliminate board conflicts. The pull-up value is nominally 50 k.
MAX 7000AE devices have an enhanced ISP algorithm for faster
programming. These devices also offer an ISP_Done bit that provides safe
operation when in-system programming is interrupted. This ISP_Done
bit, which is the last bit programmed, prevents all I/O pins from driving
until the bit is programmed. This feature is only available in EPM7032AE,
EPM7064AE, EPM7128AE, EPM7256AE, and EPM7512AE devices.
ISP simplifies the manufacturing flow by allowing devices to be mounted
on a PCB with standard pick-and-place equipment before they are
programmed. MAX 7000A devices can be programmed by downloading
the information via in-circuit testers, embedded processors, the Altera
MasterBlaster serial/USB communications cable, ByteBlasterMV parallel
port download cable, and BitBlaster serial download cable. Programming
the devices after they are placed on the board eliminates lead damage on
high-pin-count packages (e.g., QFP packages) due to device handling.
MAX 7000A devices can be reprogrammed after a system has already
shipped to the field. For example, product upgrades can be performed in
the field via software or modem.
In-system programming can be accomplished with either an adaptive or
constant algorithm. An adaptive algorithm reads information from the
unit and adapts subsequent programming steps to achieve the fastest
possible programming time for that unit. A constant algorithm uses a pre-
defined (non-adaptive) programming sequence that does not take
advantage of adaptive algorithm programming time improvements.
Some in-circuit testers cannot program using an adaptive algorithm.
Therefore, a constant algorithm must be used. MAX 7000AE devices can
be programmed with either an adaptive or constant (non-adaptive)
algorithm. EPM7128A and EPM7256A device can only be programmed
with an adaptive algorithm; users programming these two devices on
platforms that cannot use an adaptive algorithm should use EPM7128AE
and EPM7256AE devices.
The Jam Standard Test and Programming Language (STAPL), JEDEC
standard JESD 71, can be used to program MAX 7000A devices with in-
circuit testers, PCs, or embedded processors.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| EPM7064AELC44-5 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Electrically-Erasable Complex PLD |
| EPM7064AELC44-7 | 功能描述:CPLD - 复杂可编程逻辑器件 CPLD - MAX 7000 64 Macro 36 IOs RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100 |
| EPM7064AELC84-10 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Electrically-Erasable Complex PLD |
| EPM7064AELC84-4 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Electrically-Erasable Complex PLD |
| EPM7064AELC84-5 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Electrically-Erasable Complex PLD |
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