参数资料
型号: EPM7064LC84-10
厂商: Altera
文件页数: 10/66页
文件大小: 0K
描述: IC MAX 7000 CPLD 64 84-PLCC
标准包装: 75
系列: MAX® 7000
可编程类型: 系统内可编程
最大延迟时间 tpd(1): 10.0ns
电压电源 - 内部: 4.75 V ~ 5.25 V
逻辑元件/逻辑块数目: 4
宏单元数: 64
门数: 1250
输入/输出数: 68
工作温度: 0°C ~ 70°C
安装类型: 表面贴装
封装/外壳: 84-LCC(J 形引线)
供应商设备封装: 84-PLCC(29.31x29.31)
包装: 管件
其它名称: 544-2304-5
18
Altera Corporation
MAX 7000 Programmable Logic Device Family Data Sheet
Programming Times
The time required to implement each of the six programming stages can
be broken into the following two elements:
A pulse time to erase, program, or read the EEPROM cells.
A shifting time based on the test clock (TCK) frequency and the
number of TCK cycles to shift instructions, address, and data into the
device.
By combining the pulse and shift times for each of the programming
stages, the program or verify time can be derived as a function of the TCK
frequency, the number of devices, and specific target device(s). Because
different ISP-capable devices have a different number of EEPROM cells,
both the total fixed and total variable times are unique for a single device.
Programming a Single MAX 7000S Device
The time required to program a single MAX 7000S device in-system can
be calculated from the following formula:
where: tPROG
= Programming time
tPPULSE
= Sum of the fixed times to erase, program, and
verify the EEPROM cells
CyclePTCK =Number of TCK cycles to program a device
fTCK
= TCK frequency
The ISP times for a stand-alone verification of a single MAX 7000S device
can be calculated from the following formula:
where: tVER
=Verify time
tVPULSE
= Sum of the fixed times to verify the EEPROM cells
CycleVTCK =Number of TCK cycles to verify a device
tPROG
tPPULSE
CyclePTCK
fTCK
--------------------------------
+
=
tVER
tVPULSE
CycleVTCK
fTCK
--------------------------------
+
=
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EPM7064LC84-7 功能描述:CPLD - 复杂可编程逻辑器件 CPLD - MAX 7000 64 Macro 68 IOs RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100