参数资料
型号: EPM7064SLC44-5
厂商: Altera
文件页数: 13/66页
文件大小: 0K
描述: IC MAX 7000 CPLD 64 44-PLCC
标准包装: 390
系列: MAX® 7000
可编程类型: 系统内可编程
最大延迟时间 tpd(1): 5.0ns
电压电源 - 内部: 4.75 V ~ 5.25 V
逻辑元件/逻辑块数目: 4
宏单元数: 64
门数: 1250
输入/输出数: 36
工作温度: 0°C ~ 70°C
安装类型: 表面贴装
封装/外壳: 44-LCC(J 形引线)
供应商设备封装: 44-PLCC(16.58x16.58)
包装: 管件
其它名称: 544-2013
544-2013-5
544-2013-ND
EPM7064SLC44-5-ND
20
Altera Corporation
MAX 7000 Programmable Logic Device Family Data Sheet
Programmable
Speed/Power
Control
MAX 7000 devices offer a power-saving mode that supports low-power
operation across user-defined signal paths or the entire device. This
feature allows total power dissipation to be reduced by 50% or more,
because most logic applications require only a small fraction of all gates to
operate at maximum frequency.
The designer can program each individual macrocell in a MAX 7000
device for either high-speed (i.e., with the Turbo BitTM option turned on)
or low-power (i.e., with the Turbo Bit option turned off) operation. As a
result, speed-critical paths in the design can run at high speed, while the
remaining paths can operate at reduced power. Macrocells that run at low
power incur a nominal timing delay adder (tLPA) for the tLAD, tLAC, tIC,
tEN, and tSEXP, tACL, and tCPPW parameters.
Output
Configuration
MAX 7000 device outputs can be programmed to meet a variety of
system-level requirements.
MultiVolt I/O Interface
MAX 7000 devices—except 44-pin devices—support the MultiVolt I/O
interface feature, which allows MAX 7000 devices to interface with
systems that have differing supply voltages. The 5.0-V devices in all
packages can be set for 3.3-V or 5.0-V I/O pin operation. These devices
have one set of VCC pins for internal operation and input buffers
(VCCINT), and another set for I/O output drivers (VCCIO).
The VCCINT pins must always be connected to a 5.0-V power supply.
With a 5.0-V VCCINT level, input voltage thresholds are at TTL levels, and
are therefore compatible with both 3.3-V and 5.0-V inputs.
The VCCIO pins can be connected to either a 3.3-V or a 5.0-V power
supply, depending on the output requirements. When the VCCIO pins are
connected to a 5.0-V supply, the output levels are compatible with 5.0-V
systems. When VCCIO is connected to a 3.3-V supply, the output high is
3.3 V and is therefore compatible with 3.3-V or 5.0-V systems. Devices
operating with VCCIO levels lower than 4.75 V incur a nominally greater
timing delay of tOD2 instead of tOD1.
Open-Drain Output Option (MAX 7000S Devices Only)
MAX 7000S devices provide an optional open-drain (functionally
equivalent to open-collector) output for each I/O pin. This open-drain
output enables the device to provide system-level control signals (e.g.,
interrupt and write enable signals) that can be asserted by any of several
devices. It can also provide an additional wired-OR plane.
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EPM7064SLC44-7 功能描述:CPLD - 复杂可编程逻辑器件 CPLD - MAX 7000 64 Macro 36 IOs RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100
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