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参数资料
| 型号： | EPM7064SLC44-5 |
| 厂商： | Altera |
| 文件页数： | 8/66页 |
| 文件大小： | 0K |
| 描述： | IC MAX 7000 CPLD 64 44-PLCC |
| 标准包装： | 390 |
| 系列： | MAX® 7000 |
| 可编程类型： | 系统内可编程 |
| 最大延迟时间 tpd(1)： | 5.0ns |
| 电压电源 - 内部： | 4.75 V ~ 5.25 V |
| 逻辑元件/逻辑块数目： | 4 |
| 宏单元数： | 64 |
| 门数： | 1250 |
| 输入/输出数： | 36 |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 44-LCC（J 形引线） |
| 供应商设备封装： | 44-PLCC（16.58x16.58） |
| 包装： | 管件 |
| 其它名称： | 544-2013 544-2013-5 544-2013-ND EPM7064SLC44-5-ND |
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16
Altera Corporation
MAX 7000 Programmable Logic Device Family Data Sheet
When the tri-state buffer control is connected to ground, the output is
tri-stated (high impedance) and the I/O pin can be used as a dedicated
input. When the tri-state buffer control is connected to VCC, the output is
enabled.
The MAX 7000 architecture provides dual I/O feedback, in which
macrocell and pin feedbacks are independent. When an I/O pin is
configured as an input, the associated macrocell can be used for buried
logic.
In-System
Programma-
bility (ISP)
MAX 7000S devices are in-system programmable via an
industry-standard 4-pin Joint Test Action Group (JTAG) interface (IEEE
Std. 1149.1-1990). ISP allows quick, efficient iterations during design
development and debugging cycles. The MAX 7000S architecture
internally generates the high programming voltage required to program
EEPROM cells, allowing in-system programming with only a single 5.0 V
power supply. During in-system programming, the I/O pins are tri-stated
and pulled-up to eliminate board conflicts. The pull-up value is nominally
50 k.
ISP simplifies the manufacturing flow by allowing devices to be mounted
on a printed circuit board with standard in-circuit test equipment before
they are programmed. MAX 7000S devices can be programmed by
downloading the information via in-circuit testers (ICT), embedded
processors, or the Altera MasterBlaster, ByteBlasterMV, ByteBlaster,
BitBlaster download cables. (The ByteBlaster cable is obsolete and is
replaced by the ByteBlasterMV cable, which can program and configure
2.5-V, 3.3-V, and 5.0-V devices.) Programming the devices after they are
placed on the board eliminates lead damage on high-pin-count packages
(e.g., QFP packages) due to device handling and allows devices to be
reprogrammed after a system has already shipped to the field. For
example, product upgrades can be performed in the field via software or
modem.
In-system programming can be accomplished with either an adaptive or
constant algorithm. An adaptive algorithm reads information from the
unit and adapts subsequent programming steps to achieve the fastest
possible programming time for that unit. Because some in-circuit testers
cannot support an adaptive algorithm, Altera offers devices tested with a
constant algorithm. Devices tested to the constant algorithm have an “F”
suffix in the ordering code.
The JamTM Standard Test and Programming Language (STAPL) can be
used to program MAX 7000S devices with in-circuit testers, PCs, or
embedded processor.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| EPM7064SLC445F | 制造商:ALTERA 功能描述:New |
| EPM7064SLC44-5N | 功能描述:CPLD - 复杂可编程逻辑器件 CPLD - MAX 7000 64 Macro 36 IOs RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100 |
| EPM7064SLC44-6 | 功能描述:CPLD - 复杂可编程逻辑器件 CPLD - MAX 7000 64 Macro 36 IOs RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100 |
| EPM7064SLC44-7 | 功能描述:CPLD - 复杂可编程逻辑器件 CPLD - MAX 7000 64 Macro 36 IOs RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100 |
| EPM7064SLC44-7N | 功能描述:CPLD - 复杂可编程逻辑器件 CPLD - MAX 7000 64 Macro 36 IOs RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100 |
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