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参数资料
| 型号： | EPM7128AETC100-4 |
| 厂商： | ALTERA CORP |
| 元件分类： | PLD |
| 英文描述： | EE PLD, 4.5 ns, PQFP100 |
| 封装： | TQFP-100 |
| 文件页数： | 34/51页 |
| 文件大小： | 1559K |
| 代理商： | EPM7128AETC100-4 |
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598
Altera Corporation
MAX 7000A Programmable Logic Device Family Data Sheet
Preliminary Information
The MAX 7000A architecture supports 100% TTL emulation and high-
density integration of SSI, MSI, and LSI logic functions. It easily integrates
multiple devices ranging from PALs, GALs, and 22V10s to MACH, and
pLSI devices. MAX 7000A devices are available in a wide range of
packages, including PLCC, BGA, FineLine BGA, PQFP, and TQFP
packages. See Table 3.
Notes:
(1)
Contact Altera for up-to-date information on available device package options.
(2)
When the IEEE Std. 1149.1 (JTAG) interface is used for in-system programming or boundary-scan testing, four I/O
pins become JTAG pins.
(3)
All FineLine BGA packages are footprint-compatible via the SameFrame feature. Therefore, designers can design a
board to support a variety of devices, providing a flexible migration path across densities and pin counts. Device
migration is fully supported by Altera development tools. See “SameFrame Pin-Outs” on page 608 for more details.
MAX 7000A devices use CMOS EEPROM cells to implement logic
functions. The user-configurable MAX 7000A architecture accommodates
a variety of independent combinatorial and sequential logic functions.
The devices can be reprogrammed for quick and efficient iterations
during design development and debug cycles, and can be programmed
and erased up to 100 times.
MAX 7000A devices contain from 32 to 512 macrocells that are combined
into groups of 16 macrocells, called logic array blocks (LABs). Each
macrocell has a programmable-AND/fixed-OR array and a configurable
register with independently programmable clock, clock enable, clear, and
preset functions. To build complex logic functions, each macrocell can be
supplemented with both shareable expander product terms and high-
speed parallel expander product terms to provide up to 32 product terms
per macrocell.
Table 3. MAX 7000A Maximum User I/O Pins
Device
44-Pin
PLCC
44-Pin
TQFP
84-Pin
PLCC
100-Pin
TQFP
100-Pin
FineLine
BGA
144-Pin
TQFP
208-Pin
PQFP
256-Pin
BGA
256-Pin
FineLine
BGA
EPM7032AE
36
EPM7064AE
36
68
EPM7128A
68
84
100
EPM7128AE
68
84
100
EPM7256A
84
120
164
EPM7256AE
84
120
164
EPM7512AE
120
176
212
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|---|---|
| EPM7128AETC100-6 | EE PLD, 6 ns, PQFP100 |
| EPM7128AETI100-6 | EE PLD, 6 ns, PQFP100 |
| EPM7256AETC100-6 | EE PLD, 6 ns, PQFP100 |
| EPM7256AETI100-6 | EE PLD, 6 ns, PQFP100 |
| EPM7128AETC144-4 | EE PLD, 4.5 ns, PQFP144 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| EPM7128AETC100-5 | 功能描述:CPLD - 复杂可编程逻辑器件 CPLD - MAX 7000 128 Macro 84 IOs RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100 |
| EPM7128AETC100-5N | 功能描述:CPLD - 复杂可编程逻辑器件 CPLD - MAX 7000 128 Macro 84 IOs RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100 |
| EPM7128AETC100-7 | 功能描述:CPLD - 复杂可编程逻辑器件 CPLD - MAX 7000 128 Macro 84 IOs RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100 |
| EPM7128AETC1007N | 制造商:Altera Corporation 功能描述: |
| EPM7128AETC100-7N | 功能描述:CPLD - 复杂可编程逻辑器件 CPLD - MAX 7000 128 Macro 84 IOs RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100 |
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