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参数资料
| 型号： | EPM7128AETI144-6 |
| 厂商： | ALTERA CORP |
| 元件分类： | PLD |
| 英文描述： | EE PLD, 6 ns, PQFP144 |
| 封装： | TQFP-144 |
| 文件页数： | 14/51页 |
| 文件大小： | 1559K |
| 代理商： | EPM7128AETI144-6 |
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Altera Corporation
615
MAX 7000A Programmable Logic Device Family Data Sheet
Preliminary Information
Power
Sequencing &
Hot-Socketing
Because MAX 7000A family devices can be used in a mixed-voltage
environment, they have been designed specifically to tolerate any possible
power-up sequence. The VCCIO and VCCINT power planes can be powered
in any order.
Signals can be driven into MAX 7000A devices before and during power
up without damaging the device. Additionally, MAX 7000A devices do
not drive out during power up. Once operating conditions are reached,
MAX 7000A devices operate as specified by the user.
Design Security
All MAX 7000A devices contain a programmable security bit that controls
access to the data programmed into the device. When this bit is
programmed, a design implemented in the device cannot be copied or
retrieved. This feature provides a high level of design security, because
programmed data within EEPROM cells is invisible. The security bit that
controls this function, as well as all other programmed data, is reset only
when the device is reprogrammed.
Generic Testing
MAX 7000A devices are fully functionally tested. Complete testing of
each programmable EEPROM bit and all internal logic elements ensures
100% programming yield. AC test measurements are taken under
conditions equivalent to those shown in Figure 9. Test patterns can be
used and then erased during early stages of the production flow.
Figure 9. MAX 7000A AC Test Conditions
VCC
To Test
System
C1 (includes JIG
capacitance)
Device input
rise and fall
times < 2 ns
Device
Output
703
[521
]
8,060
[481
]
Power supply transients can affect AC
measurements. Simultaneous transitions
of multiple outputs should be avoided for
accurate measurement. Threshold tests
must not be performed under AC
conditions. Large-amplitude, fast-ground-
current transients normally occur as the
device outputs discharge the load
capacitances. When these transients ow
through the parasitic inductance between
the device ground pin and the test system
ground, signicant reductions in
observable noise immunity can result.
Numbers in brackets are for 2.5-V
outputs. Numbers without brackets are for
3.3-V devices or outputs.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| EPM7128AETI144-7 | 功能描述:CPLD - 复杂可编程逻辑器件 CPLD - MAX 7000 128 Macro 36 IOs RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100 |
| EPM7128AETI144-7N | 功能描述:CPLD - 复杂可编程逻辑器件 CPLD - MAX 7000 128 Macro 36 IOs RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100 |
| EPM7128AEUC169-10 | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Altera Corporation 功能描述: |
| EPM7128AEUC169-5 | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Altera Corporation 功能描述: |
| EPM7128AEUC169-7 | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Altera Corporation 功能描述: |
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