参数资料
型号: EPM9320ALC84-10
文件页数: 25/42页
文件大小: 489K
代理商: EPM9320ALC84-10
Altera Corporation
31
MAX 9000 Programmable Logic Device Family Data Sheet
Table 20. IOC Delays
Symbol
Parameter
Conditions
Speed Grade
Unit
-10
-15
-20
Min
Max
Min
Max
Min
Max
tIODR
I/O row output data delay
0.2
1.5
ns
tIODC
I/O column output data delay
0.4
0.2
1.5
ns
tIOC
I/O control delay
0.5
1.0
2.0
ns
tIORD
I/O register clock-to-output
delay
0.6
1.0
1.5
ns
tIOCOMB
I/O combinatorial delay
0.2
1.0
1.5
ns
tIOSU
I/O register setup time before
clock
2.0
4.0
5.0
ns
tIOH
I/O register hold time after
clock
1.0
ns
tIOCLR
I/O register clear delay
1.5
3.0
ns
tIOFD
I/O register feedback delay
0.0
0.5
ns
tINREG
I/O input pad and buffer to I/O
register delay
3.5
4.5
5.5
ns
tINCOMB
I/O input pad and buffer to row
and column delay
1.5
2.0
2.5
ns
tOD1
Output buffer and pad delay,
Slow slew rate = off,
V CCIO = 5.0 V
C1 = 35 pF
1.8
2.5
ns
tOD2
Output buffer and pad delay,
Slow slew rate = off,
V CCIO = 3.3 V
C1 = 35 pF
2.3
3.5
ns
tOD3
Output buffer and pad delay,
Slow slew rate = on,
V CCIO = 5.0 V or 3.3 V
C1 = 35 pF
8.3
10.0
10.5
ns
tXZ
Output buffer disable delay
C1 = 5 pF
2.5
ns
tZX1
Output buffer enable delay,
Slow slew rate = off,
V CCIO = 5.0 V
C1 = 35 pF
2.5
ns
tZX2
Output buffer enable delay,
Slow slew rate = off,
V CCIO = 3.3 V
C1 = 35 pF
3.0
3.5
ns
tZX3
Output buffer enable delay,
Slow slew rate = on,
V CCIO = 3.3 V or 5.0 V
C1 = 35 pF
9.0
10.0
10.5
ns
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